GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/msi/ms7d25: Disable PCIe hotplug 

The support for the board has stabilized and PCIe ports have been
tested with many devices. Although hotplug is not commonly used
and it seems pointless to keep it enabled, so disable it.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I338c55cb57d971badd08235b71626a710fafb829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This commit is contained in:
Michał Żygowski 2022-11-09 14:53:31 +01:00 committed by Felix Singer
parent 60ee6fa398
commit 115aa9421d
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/mainboard/msi/ms7d25/devicetree.cb
View File

@ -98,7 +98,7 @@ chip soc/intel/alderlake
register "cpu_pcie_rp[CPU_RP(2)]" = "{ register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 0, .clk_src = 0,
.clk_req = 0, .clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG, .flags = PCIE_RP_LTR | PCIE_RP_AER,
.PcieRpL1Substates = L1_SS_L1_2, .PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_aspm = ASPM_L0S_L1, .pcie_rp_aspm = ASPM_L0S_L1,
}" }"
@ -141,7 +141,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(1)]" = "{ register "pch_pcie_rp[PCH_RP(1)]" = "{
.clk_src = 10, .clk_src = 10,
.clk_req = 10, .clk_req = 10,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.PcieRpL1Substates = L1_SS_L1_2, .PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_aspm = ASPM_L0S_L1, .pcie_rp_aspm = ASPM_L0S_L1,
}" }"
@ -152,7 +152,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(2)]" = "{ register "pch_pcie_rp[PCH_RP(2)]" = "{
.clk_src = 17, .clk_src = 17,
.clk_req = 17, .clk_req = 17,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.PcieRpL1Substates = L1_SS_L1_2, .PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_aspm = ASPM_L0S_L1, .pcie_rp_aspm = ASPM_L0S_L1,
}" }"
@ -174,7 +174,7 @@ chip soc/intel/alderlake
register "pch_pcie_rp[PCH_RP(5)]" = "{ register "pch_pcie_rp[PCH_RP(5)]" = "{
.clk_src = 15, .clk_src = 15,
.clk_req = 15, .clk_req = 15,
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG | PCIE_RP_CLK_REQ_DETECT, .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT,
.PcieRpL1Substates = L1_SS_L1_2, .PcieRpL1Substates = L1_SS_L1_2,
.pcie_rp_aspm = ASPM_L0S_L1, .pcie_rp_aspm = ASPM_L0S_L1,
}" }"