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mb/google/skyrim/var/winterhold: Enable RTD3 support for eMMC as NVMe 

winterhold/whiterun has different H/W topology to skyrim that the eMMC device
is on a different GPP:
skyrim: GPP1 -> SD
winterhold : GPP1 -> eMMC

BUG=b:263763288
BRANCH=none
TEST=s0i3 stress over 2500 cycles.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ie6af4287057c6befa0b787ac28d7898166401b29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Chris.Wang 2022-12-28 14:33:44 +08:00 committed by Martin Roth
parent b3a28c3a66
commit 1162f7a1fe
1 changed files with 15 additions and 0 deletions
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15
src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
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@ -99,6 +99,21 @@ chip soc/amd/mendocino
register "stt_skin_temp_apu_F" = "0x3200" register "stt_skin_temp_apu_F" = "0x3200"
device domain 0 on device domain 0 on
device ref gpp_bridge_1 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # eMMC
device ref gpp_bridge_2 on
# Required so the NVMe gets placed into D3 when entering S0i3.
chip drivers/pcie/rtd3/device
register "name" = ""NVME""
device pci 00.0 on end
end
end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref xhci_1 on # XHCI1 controller device ref xhci_1 on # XHCI1 controller
chip drivers/usb/acpi chip drivers/usb/acpi