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soc/intel/alderlake: Enable Energy/Performance Bias control 

According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL
must be set to be able to set the Energy/Performance Bias using MSR
IA32_ENERGY_PERF_BIAS.

Note that since this bit was not set until this patch, the
`set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in
`soc_core_init()` was systematically failing.

BRANCH=firmware-brya-14505.B
BUG=b:239853069
TEST=verify that EPB is set by coreboot

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jeremy Compostella 2022-07-21 15:40:03 -07:00 committed by Paul Fagerburg
parent ccbf27cbe7
commit 117770d324
1 changed files with 2 additions and 1 deletions
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3
src/soc/intel/alderlake/cpu.c
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@ -76,10 +76,11 @@ static void configure_misc(void)
msr.hi = 0; msr.hi = 0;
wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
/* Enable PROCHOT */ /* Enable PROCHOT and Energy/Performance Bias control */
msr = rdmsr(MSR_POWER_CTL); msr = rdmsr(MSR_POWER_CTL);
msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input */
msr.lo |= (1 << 23); /* Lock it */ msr.lo |= (1 << 23); /* Lock it */
msr.lo |= (1 << 18); /* Energy/Performance Bias control */
wrmsr(MSR_POWER_CTL, msr); wrmsr(MSR_POWER_CTL, msr);
} }