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mb/**/devicetree.cb: Remove untrue comments 

Even if they were corrected, they just rephrase the code.

Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This commit is contained in:
Angel Pons 2020-01-01 18:05:08 +01:00 committed by Nico Huber
parent 9f363fc85a
commit 118b18e63a
7 changed files with 0 additions and 8 deletions
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1
src/mainboard/asrock/h110m/devicetree.cb
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@ -16,7 +16,6 @@
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"

2
src/mainboard/facebook/monolith/devicetree.cb
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@ -1,6 +1,5 @@
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
@ -24,7 +23,6 @@ chip soc/intel/skylake
# Enable "Intel Speed Shift Technology"
register "speed_shift_enable" = "1"
# Enable DPTF
register "dptf_enable" = "0"
# FSP Configuration

1
src/mainboard/intel/saddlebrook/devicetree.cb
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@ -15,7 +15,6 @@
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"

1
src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
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@ -8,7 +8,6 @@ chip soc/intel/skylake
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"

1
src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
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@ -8,7 +8,6 @@ chip soc/intel/skylake
register "gpu_pch_backlight_pwm_hz" = "200"
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"

1
src/mainboard/razer/blade_stealth_kbl/devicetree.cb
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@ -1,5 +1,4 @@
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s3_enable_ac" = "0"
register "deep_s3_enable_dc" = "0"
register "deep_s5_enable_ac" = "0"

1
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
View File

@ -1,6 +1,5 @@
chip soc/intel/skylake
# Enable deep Sx states
register "deep_s5_enable_ac" = "0"
register "deep_s5_enable_dc" = "0"
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"