haswell: Export functions for CPU family+model and stepping
These are needed to enable workarounds/features on specific CPU types and stepping. The older northbridge function and defines from sandybridge/ivybridge are removed. Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61333 Commit-Queue: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4355 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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@ -24,6 +24,18 @@
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#include <arch/cpu.h>
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#include <arch/cpu.h>
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/* Haswell CPU types */
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#define HASWELL_FAMILY_MOBILE 0x306c0
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#define HASWELL_FAMILY_ULT 0x40650
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/* Haswell CPU steppings */
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#define HASWELL_STEPPING_MOBILE_A0 1
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#define HASWELL_STEPPING_MOBILE_B0 2
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#define HASWELL_STEPPING_MOBILE_C0 3
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#define HASWELL_STEPPING_MOBILE_D0 4
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#define HASWELL_STEPPING_ULT_B0 0
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#define HASWELL_STEPPING_ULT_C0 1
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/* Haswell bus clock is fixed at 100MHz */
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/* Haswell bus clock is fixed at 100MHz */
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#define HASWELL_BCLK 100
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#define HASWELL_BCLK 100
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@ -219,6 +231,11 @@ struct ramstage_cache {
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char program[0];
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char program[0];
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} __attribute__((packed));
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} __attribute__((packed));
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/* CPU identification */
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int haswell_family_model(void);
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int haswell_stepping(void);
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int haswell_is_ult(void);
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#endif
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#endif
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#endif
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#endif
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@ -207,13 +207,23 @@ static const u8 power_limit_time_msr_to_sec[] = {
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[0x11] = 128,
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[0x11] = 128,
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};
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};
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int haswell_family_model(void)
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{
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return cpuid_eax(1) & 0x0fff0ff0;
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}
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int haswell_stepping(void)
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{
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return cpuid_eax(1) & 0xf;
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}
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/* Dynamically determine if the part is ULT. */
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/* Dynamically determine if the part is ULT. */
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static int is_ult(void)
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int haswell_is_ult(void)
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{
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{
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static int ult = -1;
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static int ult = -1;
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if (ult < 0)
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if (ult < 0)
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ult = (cpuid_eax(1) > 0x40650);
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ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT);
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return ult;
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return ult;
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}
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}
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@ -308,7 +318,7 @@ static void initialize_vr_config(void)
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msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */
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msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */
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msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
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msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
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if (is_ult())
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if (haswell_is_ult())
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msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
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msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */
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/* Leave the max instantaneous current limit (12:0) to default. */
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/* Leave the max instantaneous current limit (12:0) to default. */
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wrmsr(MSR_VR_CURRENT_CONFIG, msr);
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wrmsr(MSR_VR_CURRENT_CONFIG, msr);
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@ -334,7 +344,7 @@ static void initialize_vr_config(void)
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wrmsr(MSR_VR_MISC_CONFIG, msr);
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wrmsr(MSR_VR_MISC_CONFIG, msr);
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/* Configure VR_MISC_CONFIG2 MSR. */
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/* Configure VR_MISC_CONFIG2 MSR. */
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if (is_ult()) {
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if (haswell_is_ult()) {
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msr = rdmsr(MSR_VR_MISC_CONFIG2);
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msr = rdmsr(MSR_VR_MISC_CONFIG2);
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msr.lo &= ~0xffff;
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msr.lo &= ~0xffff;
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/* Allow CPU to control minimum voltage completely (15:8) and
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/* Allow CPU to control minimum voltage completely (15:8) and
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@ -521,7 +531,7 @@ static void configure_c_states(void)
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wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
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wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
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/* Haswell ULT only supoprts the 3-5 latency response registers.*/
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/* Haswell ULT only supoprts the 3-5 latency response registers.*/
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if (is_ult()) {
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if (haswell_is_ult()) {
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/* C-state Interrupt Response Latency Control 3 - package C8 */
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/* C-state Interrupt Response Latency Control 3 - package C8 */
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msr.hi = 0;
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msr.hi = 0;
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msr.lo = IRTL_VALID | IRTL_1024_NS |
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msr.lo = IRTL_VALID | IRTL_1024_NS |
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@ -698,7 +708,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
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initialize_vr_config();
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initialize_vr_config();
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if (is_ult()) {
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if (haswell_is_ult()) {
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calibrate_24mhz_bclk();
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calibrate_24mhz_bclk();
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configure_pch_power_sharing();
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configure_pch_power_sharing();
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}
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}
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@ -26,23 +26,6 @@
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#define HASWELL_DESKTOP 1
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#define HASWELL_DESKTOP 1
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#define HASWELL_SERVER 2
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#define HASWELL_SERVER 2
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/* Device ID for SandyBridge and IvyBridge */
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#define BASE_REV_SNB 0x00
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#define BASE_REV_IVB 0x50
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#define BASE_REV_MASK 0x50
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/* SandyBridge CPU stepping */
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#define SNB_STEP_D0 (BASE_REV_SNB + 5) /* Also J0 */
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#define SNB_STEP_D1 (BASE_REV_SNB + 6)
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#define SNB_STEP_D2 (BASE_REV_SNB + 7) /* Also J1/Q0 */
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/* IvyBridge CPU stepping */
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#define IVB_STEP_A0 (BASE_REV_IVB + 0)
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#define IVB_STEP_B0 (BASE_REV_IVB + 2)
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#define IVB_STEP_C0 (BASE_REV_IVB + 4)
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#define IVB_STEP_K0 (BASE_REV_IVB + 5)
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#define IVB_STEP_D0 (BASE_REV_IVB + 6)
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/* Intel Enhanced Debug region */
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/* Intel Enhanced Debug region */
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#define IED_SIZE CONFIG_IED_REGION_SIZE
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#define IED_SIZE CONFIG_IED_REGION_SIZE
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@ -215,7 +198,6 @@ struct ied_header {
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#ifdef __SMM__
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#ifdef __SMM__
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void intel_northbridge_haswell_finalize_smm(void);
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void intel_northbridge_haswell_finalize_smm(void);
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#else /* !__SMM__ */
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#else /* !__SMM__ */
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int bridge_silicon_revision(void);
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void haswell_early_initialization(int chipset_type);
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void haswell_early_initialization(int chipset_type);
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void haswell_late_initialization(void);
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void haswell_late_initialization(void);
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@ -39,20 +39,6 @@
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#include "chip.h"
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#include "chip.h"
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#include "haswell.h"
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#include "haswell.h"
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static int bridge_revision_id = -1;
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int bridge_silicon_revision(void)
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{
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if (bridge_revision_id < 0) {
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uint8_t stepping = cpuid_eax(1) & 0xf;
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uint8_t bridge_id = pci_read_config16(
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dev_find_slot(0, PCI_DEVFN(0, 0)),
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PCI_DEVICE_ID) & 0xf0;
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bridge_revision_id = bridge_id | stepping;
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}
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return bridge_revision_id;
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}
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static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
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{
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{
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u32 pciexbar_reg;
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u32 pciexbar_reg;
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