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soc/intel/cnl: Configure FSP option PcieRpSlotImplemented

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Allow configuring FSP option PcieRpSlotImplemented. Also, update all
related devicetrees and configure PcieRpSlotImplemented to keep the
current behaviour.

Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Nico Huber 2019-10-02 16:02:06 +02:00 committed by Nico Huber
parent 2b9035ed6e
commit 119ace0908
23 changed files with 171 additions and 50 deletions
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2
src/mainboard/google/drallion/variants/drallion/devicetree.cb
View file

@ -444,12 +444,14 @@ chip soc/intel/cannonlake
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
register "PcieRpSlotImplemented[8]" = "1"
end # PCI Express Port 9
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[12]" = "1"
end # PCI Express Port 13 (x4)
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1

5
src/mainboard/google/hatch/variants/baseboard/devicetree.cb
View file

@ -329,7 +329,9 @@ chip soc/intel/cannonlake
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9 (X4 NVME)
device pci 1d.0 on # PCI Express Port 9 (X4 NVME)
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
@ -339,6 +341,7 @@ chip soc/intel/cannonlake
register "wake" = "GPE0_DW1_01"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[13]" = "1"
end # PCI Express Port 14 (x4)
device pci 1e.0 on end # UART #0
device pci 1e.1 off end # UART #1

5
src/mainboard/google/hatch/variants/duffy/overridetree.cb
View file

@ -394,8 +394,11 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/faffy/overridetree.cb
View file

@ -401,8 +401,11 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/kaisa/overridetree.cb
View file

@ -394,8 +394,11 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/noibat/overridetree.cb
View file

@ -309,8 +309,11 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/puff/overridetree.cb
View file

@ -333,8 +333,11 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1
end

5
src/mainboard/google/hatch/variants/wyvern/overridetree.cb
View file

@ -328,8 +328,11 @@ chip soc/intel/cannonlake
register "device_index" = "0"
device pci 00.0 on end
end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe)
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1
end

6
src/mainboard/google/sarien/variants/arcada/devicetree.cb
View file

@ -377,8 +377,11 @@ chip soc/intel/cannonlake
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
register "PcieRpSlotImplemented[9]" = "1"
end # PCI Express Port 10
device pci 1d.2 on end # PCI Express Port 11
device pci 1d.2 on # PCI Express Port 11
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on
chip drivers/generic/bayhub
@ -386,6 +389,7 @@ chip soc/intel/cannonlake
device pci 00.0 on end
end
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[12]" = "1"
end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1

14
src/mainboard/google/sarien/variants/sarien/devicetree.cb
View file

@ -385,22 +385,29 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 off end # eMMC
device pci 1c.0 on end # PCI Express Port 1 (USB)
device pci 1c.0 on # PCI Express Port 1 (USB)
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.1 off end # PCI Express Port 2 (USB)
device pci 1c.2 off end # PCI Express Port 3 (USB)
device pci 1c.3 off end # PCI Express Port 4 (USB)
device pci 1c.4 off end # PCI Express Port 5 (USB)
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on end # PCI Express Port 8
device pci 1c.7 on # PCI Express Port 8
register "PcieRpSlotImplemented[7]" = "1"
end
device pci 1d.0 on
chip drivers/generic/bayhub
register "power_saving" = "1"
device pci 00.0 on end
end
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X"
register "PcieRpSlotImplemented[8]" = "1"
end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10
device pci 1d.1 on # PCI Express Port 10
register "PcieRpSlotImplemented[9]" = "1"
end
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on
@ -409,6 +416,7 @@ chip soc/intel/cannonlake
device pci 00.0 on end
end
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[12]" = "1"
end # PCI Express Port 13 (x4)
device pci 1e.0 off end # UART #0
device pci 1e.1 off end # UART #1

12
src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
View file

@ -124,12 +124,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
View file

@ -140,12 +140,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/coffeelake_rvp/variants/cfl_h/overridetree.cb
View file

@ -99,12 +99,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.4 off end # PCI Express Port 13
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15

32
src/mainboard/intel/coffeelake_rvp/variants/cfl_s/overridetree.cb
View file

@ -107,12 +107,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5 (Not available on PCH-H)
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1
device pci 1c.4 on end # PCI Express Port 5
device pci 1c.0 on # PCI Express Port 1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9 x4 SLOT 1
device pci 1d.0 on # PCI Express Port 9 x4 SLOT 1
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
@ -120,11 +126,21 @@ chip soc/intel/cannonlake
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16
device pci 1b.0 on end # PCI Express Port 17
device pci 1b.1 on end # PCI Express Port 18
device pci 1b.2 on end # PCI Express Port 19
device pci 1b.3 on end # PCI Express Port 20
device pci 1b.4 on end # PCI Express Port 21 X4 SLOT 2
device pci 1b.0 on # PCI Express Port 17
register "PcieRpSlotImplemented[16]" = "1"
end
device pci 1b.1 on # PCI Express Port 18
register "PcieRpSlotImplemented[17]" = "1"
end
device pci 1b.2 on # PCI Express Port 19
register "PcieRpSlotImplemented[18]" = "1"
end
device pci 1b.3 on # PCI Express Port 20
register "PcieRpSlotImplemented[19]" = "1"
end
device pci 1b.4 on # PCI Express Port 21 X4 SLOT 2
register "PcieRpSlotImplemented[20]" = "1"
end
device pci 1e.1 off end # UART #1
device pci 1f.6 on end # GbE
end

12
src/mainboard/intel/coffeelake_rvp/variants/cfl_u/overridetree.cb
View file

@ -84,12 +84,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/coffeelake_rvp/variants/cml_u/overridetree.cb
View file

@ -94,12 +94,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

12
src/mainboard/intel/coffeelake_rvp/variants/whl_u/overridetree.cb
View file

@ -78,12 +78,18 @@ chip soc/intel/cannonlake
device pci 19.1 off end # I2C #5
device pci 19.2 on end # UART #2
device pci 1a.0 on end # eMMC
device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1
device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN
device pci 1c.0 on # PCI Express Port 1 x4 SLOT1
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 off end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12

1
src/mainboard/prodrive/hermes/devicetree.cb
View file

@ -35,6 +35,7 @@ chip soc/intel/cannonlake
device pci 00.0 on # Aspeed PCI Bridge
device pci 00.0 on end # Aspeed 2500 VGA
end
register "PcieRpSlotImplemented[14]" = "1"
end
device pci 1f.0 on # LPC Interface
chip drivers/pc80/tpm

27
src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb
View file

@ -183,20 +183,35 @@ chip soc/intel/cannonlake
end
device pci 1b.4 on # PCIe root port 21 (Slot 1)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[20]" = "1"
end
device pci 1c.0 on # PCIe root port 1 (Slot 3)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT3" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[0]" = "1"
end
device pci 1c.4 on # PCIe root port 5 (PHY 3)
register "PcieRpSlotImplemented[4]" = "1"
end
device pci 1c.5 on # PCIe root port 6 (PHY 4)
register "PcieRpSlotImplemented[5]" = "1"
end
device pci 1c.6 on # PCIe root port 7 (PHY 2)
register "PcieRpSlotImplemented[6]" = "1"
end
device pci 1c.7 on # PCIe root port 8 (PHY 1)
register "PcieRpSlotImplemented[7]" = "1"
end
device pci 1c.4 on end # PCIe root port 5 (PHY 3)
device pci 1c.5 on end # PCIe root port 6 (PHY 4)
device pci 1c.6 on end # PCIe root port 7 (PHY 2)
device pci 1c.7 on end # PCIe root port 8 (PHY 1)
device pci 1d.0 on # PCIe root port 9 (M2 M)
smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "M2 M" "SlotDataBusWidth4X"
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.5 on # PCIe root port 14 (PHY 0)
register "PcieRpSlotImplemented[13]" = "1"
end
device pci 1d.6 on # PCIe root port 15 (BMC)
register "PcieRpSlotImplemented[14]" = "1"
end
device pci 1d.5 on end # PCIe root port 14 (PHY 0)
device pci 1d.6 on end # PCIe root port 15 (BMC)
device pci 1e.0 on end # UART #0
device pci 1e.1 on end # UART #1

12
src/mainboard/purism/librem_whl/devicetree.cb
View file

@ -293,12 +293,18 @@ chip soc/intel/cannonlake
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on end # PCI Express Port 8 (WLAN)
device pci 1c.7 on # PCI Express Port 8 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
end
device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on end # PCI Express Port 10 (LAN)
device pci 1d.1 on # PCI Express Port 10 (LAN)
register "PcieRpSlotImplemented[9]" = "1"
end
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13 (NVMe)
device pci 1d.4 on # PCI Express Port 13 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16

16
src/mainboard/system76/lemp9/devicetree.cb
View file

@ -215,14 +215,22 @@ chip soc/intel/cannonlake
device pci 1c.2 off end # PCI Express Port 3
device pci 1c.3 off end # PCI Express Port 4
device pci 1c.4 off end # PCI Express Port 5
device pci 1c.5 on end # PCI Express Port 6
device pci 1c.5 on # PCI Express Port 6
register "PcieRpSlotImplemented[5]" = "1"
end
device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on end # PCI Express Port 8
device pci 1d.0 on end # PCI Express Port 9
device pci 1c.7 on # PCI Express Port 8
register "PcieRpSlotImplemented[7]" = "1"
end
device pci 1d.0 on # PCI Express Port 9
register "PcieRpSlotImplemented[8]" = "1"
end
device pci 1d.1 off end # PCI Express Port 10
device pci 1d.2 off end # PCI Express Port 11
device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on end # PCI Express Port 13
device pci 1d.4 on # PCI Express Port 13
register "PcieRpSlotImplemented[12]" = "1"
end
device pci 1d.5 off end # PCI Express Port 14
device pci 1d.6 off end # PCI Express Port 15
device pci 1d.7 off end # PCI Express Port 16

2
src/soc/intel/cannonlake/chip.h
View file

@ -185,6 +185,8 @@ struct soc_intel_cannonlake_config {
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
/* PCIe LTR(Latency Tolerance Reporting) mechanism */
uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
/* Implemented as slot or built-in? */
uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
/* Enable/Disable HotPlug support for Root Port */
uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];

2
src/soc/intel/cannonlake/fsp_params.c
View file

@ -479,6 +479,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,
sizeof(config->PcieRpLtrEnable));
memcpy(params->PcieRpSlotImplemented, config->PcieRpSlotImplemented,
sizeof(config->PcieRpSlotImplemented));
memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug,
sizeof(params->PcieRpHotPlug));