mb/gigabyte/ga-h61m-s2pv: Add ga-h61m-ds2v as a variant
Took less than 30 minutes, and booted on the first try :) Working: - Native raminit, using two 2GB DDR3-1333 DIMMs - S3 suspend/resume - USB ports and headers - EHCI Debug with an FT2232H - Gigabit Ethernet - Integrated DVI/VGA outputs (libgfxinit) - PCIe x16 for a graphics card - PCIe x1 ports - PS/2 port with a keyboard - SATA controller - Audio outputs, both front and rear - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio inputs - Non-Linux OSes - ACPI thermal zone and OS-independent fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Using 'flashrom --ifd -i bios' is asking for a failed flash! Change-Id: I467f586530e4a3b53a24b66565b5dcab5e33cf46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
Nico Huber
parent
ffcf641cc4
commit
11bf9df9ac
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@ -13,7 +13,7 @@
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## GNU General Public License for more details.
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##
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if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V
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if BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61M_DS2V || BOARD_GIGABYTE_GA_H61MA_D3V
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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@ -30,7 +30,6 @@ config BOARD_SPECIFIC_OPTIONS
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select INTEL_GMA_HAVE_VBT
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select NO_UART_ON_SUPERIO if BOARD_GIGABYTE_GA_H61MA_D3V
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config MAINBOARD_DIR
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string
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@ -39,11 +38,13 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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string
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default "ga-h61m-s2pv" if BOARD_GIGABYTE_GA_H61M_S2PV
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default "ga-h61m-ds2v" if BOARD_GIGABYTE_GA_H61M_DS2V
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default "ga-h61ma-d3v" if BOARD_GIGABYTE_GA_H61MA_D3V
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config MAINBOARD_PART_NUMBER
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string
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default "GA-H61M-S2PV" if BOARD_GIGABYTE_GA_H61M_S2PV
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default "GA-H61M-DS2V" if BOARD_GIGABYTE_GA_H61M_DS2V
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default "GA-H61MA-D3V" if BOARD_GIGABYTE_GA_H61MA_D3V
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config DEVICETREE
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@ -62,4 +63,4 @@ config USBDEBUG_HCD_INDEX # Bottom left port seen from rear
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int
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default 2
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endif # BOARD_GIGABYTE_GA_H61M_S2PV || BOARD_GIGABYTE_GA_H61MA_D3V
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endif # BOARD_GIGABYTE_GA_H61M*
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@ -1,5 +1,10 @@
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config BOARD_GIGABYTE_GA_H61M_S2PV
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bool "GA-H61M-S2PV"
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config BOARD_GIGABYTE_GA_H61M_DS2V
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bool "GA-H61M-DS2V"
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select NO_UART_ON_SUPERIO
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config BOARD_GIGABYTE_GA_H61MA_D3V
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bool "GA-H61MA-D3V"
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select NO_UART_ON_SUPERIO
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@ -0,0 +1,96 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/sandybridge
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0 on end
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device lapic 0xacac off end
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end
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end
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register "pci_mmio_size" = "2048"
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device domain 0 on
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subsystemid 0x1458 0x5000 inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PEG
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device pci 02.0 on end # iGPU
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "gen1_dec" = "0x003c0a01"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x33"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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device pci 16.0 on end # MEI #1
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 on end # HD Audio
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device pci 1c.0 on end # RP #1: PCIe x1 Port (PCIEX1_3)
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device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1)
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device pci 1c.2 off end # RP #3:
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device pci 1c.3 off end # RP #4:
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device pci 1c.4 on end # RP #4: Realtek RTL8111F GbE NIC
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device pci 1c.5 on end # RP #5: PCIe x1 Port (PCIEX1_2)
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on # LPC bridge
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chip superio/ite/it8728f
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 off end # COM1
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device pnp 2e.2 off end # COM2
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device pnp 2e.3 off end # Parallel port
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device pnp 2e.4 on # Environment Controller
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io 0x60 = 0x0a30
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io 0x62 = 0x0a20
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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end
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device pnp 2e.6 on end # Mouse
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device pnp 2e.7 on # GPIO
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irq 0x25 = 0x40
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irq 0x26 = 0xf7
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irq 0x27 = 0x10
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irq 0x2c = 0x80
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io 0x60 = 0x0000
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io 0x62 = 0x0a00
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io 0x64 = 0x0000
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irq 0x73 = 0x00
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irq 0xc1 = 0x37
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irq 0xcb = 0x00
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irq 0xf0 = 0x10
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irq 0xf1 = 0x42
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irq 0xf6 = 0x1c
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end
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device pnp 2e.a off end # CIR
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 on end # Thermal
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end
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end
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end
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@ -0,0 +1,203 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <southbridge/intel/common/gpio.h>
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO,
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.gpio1 = GPIO_MODE_GPIO,
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.gpio2 = GPIO_MODE_GPIO,
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.gpio3 = GPIO_MODE_GPIO,
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.gpio4 = GPIO_MODE_GPIO,
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.gpio5 = GPIO_MODE_GPIO,
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.gpio6 = GPIO_MODE_GPIO,
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.gpio7 = GPIO_MODE_GPIO,
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.gpio8 = GPIO_MODE_GPIO,
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.gpio9 = GPIO_MODE_NATIVE,
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.gpio10 = GPIO_MODE_NATIVE,
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.gpio11 = GPIO_MODE_NATIVE,
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.gpio12 = GPIO_MODE_GPIO,
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.gpio13 = GPIO_MODE_GPIO,
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.gpio14 = GPIO_MODE_NATIVE,
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.gpio15 = GPIO_MODE_GPIO,
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.gpio16 = GPIO_MODE_GPIO,
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.gpio17 = GPIO_MODE_GPIO,
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.gpio18 = GPIO_MODE_NATIVE,
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.gpio19 = GPIO_MODE_GPIO,
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.gpio20 = GPIO_MODE_NATIVE,
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.gpio21 = GPIO_MODE_GPIO,
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.gpio22 = GPIO_MODE_GPIO,
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.gpio23 = GPIO_MODE_NATIVE,
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.gpio24 = GPIO_MODE_GPIO,
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.gpio25 = GPIO_MODE_NATIVE,
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.gpio26 = GPIO_MODE_NATIVE,
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.gpio27 = GPIO_MODE_GPIO,
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.gpio28 = GPIO_MODE_GPIO,
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.gpio29 = GPIO_MODE_GPIO,
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.gpio30 = GPIO_MODE_NATIVE,
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.gpio31 = GPIO_MODE_GPIO,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio1 = GPIO_DIR_INPUT,
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.gpio2 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio4 = GPIO_DIR_INPUT,
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.gpio5 = GPIO_DIR_INPUT,
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.gpio6 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_OUTPUT,
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.gpio12 = GPIO_DIR_OUTPUT,
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.gpio13 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_OUTPUT,
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.gpio16 = GPIO_DIR_INPUT,
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.gpio17 = GPIO_DIR_INPUT,
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.gpio19 = GPIO_DIR_INPUT,
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.gpio21 = GPIO_DIR_INPUT,
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.gpio22 = GPIO_DIR_INPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio27 = GPIO_DIR_INPUT,
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.gpio28 = GPIO_DIR_OUTPUT,
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.gpio29 = GPIO_DIR_INPUT,
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.gpio31 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio8 = GPIO_LEVEL_HIGH,
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.gpio12 = GPIO_LEVEL_HIGH,
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.gpio15 = GPIO_LEVEL_LOW,
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.gpio24 = GPIO_LEVEL_LOW,
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.gpio28 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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.gpio24 = GPIO_RESET_RSMRST,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio13 = GPIO_INVERT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio32 = GPIO_MODE_GPIO,
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.gpio33 = GPIO_MODE_GPIO,
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.gpio34 = GPIO_MODE_GPIO,
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.gpio35 = GPIO_MODE_GPIO,
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.gpio36 = GPIO_MODE_GPIO,
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.gpio37 = GPIO_MODE_GPIO,
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.gpio38 = GPIO_MODE_GPIO,
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.gpio39 = GPIO_MODE_GPIO,
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.gpio40 = GPIO_MODE_NATIVE,
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.gpio41 = GPIO_MODE_NATIVE,
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.gpio42 = GPIO_MODE_NATIVE,
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.gpio43 = GPIO_MODE_NATIVE,
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.gpio44 = GPIO_MODE_NATIVE,
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.gpio45 = GPIO_MODE_NATIVE,
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.gpio46 = GPIO_MODE_NATIVE,
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.gpio47 = GPIO_MODE_NATIVE,
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.gpio48 = GPIO_MODE_GPIO,
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.gpio49 = GPIO_MODE_GPIO,
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.gpio50 = GPIO_MODE_NATIVE,
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.gpio51 = GPIO_MODE_NATIVE,
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.gpio52 = GPIO_MODE_NATIVE,
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.gpio53 = GPIO_MODE_NATIVE,
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.gpio54 = GPIO_MODE_NATIVE,
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.gpio55 = GPIO_MODE_NATIVE,
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.gpio56 = GPIO_MODE_NATIVE,
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.gpio57 = GPIO_MODE_GPIO,
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.gpio58 = GPIO_MODE_NATIVE,
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.gpio59 = GPIO_MODE_NATIVE,
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.gpio60 = GPIO_MODE_NATIVE,
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.gpio61 = GPIO_MODE_NATIVE,
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.gpio62 = GPIO_MODE_NATIVE,
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.gpio63 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio32 = GPIO_DIR_OUTPUT,
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.gpio33 = GPIO_DIR_OUTPUT,
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.gpio34 = GPIO_DIR_INPUT,
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.gpio35 = GPIO_DIR_OUTPUT,
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.gpio36 = GPIO_DIR_INPUT,
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.gpio37 = GPIO_DIR_INPUT,
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.gpio38 = GPIO_DIR_INPUT,
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.gpio39 = GPIO_DIR_INPUT,
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.gpio48 = GPIO_DIR_INPUT,
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.gpio49 = GPIO_DIR_INPUT,
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.gpio57 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio32 = GPIO_LEVEL_HIGH,
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.gpio33 = GPIO_LEVEL_HIGH,
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.gpio35 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_reset = {
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};
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static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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.gpio64 = GPIO_MODE_NATIVE,
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.gpio65 = GPIO_MODE_NATIVE,
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.gpio66 = GPIO_MODE_NATIVE,
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.gpio67 = GPIO_MODE_NATIVE,
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.gpio68 = GPIO_MODE_GPIO,
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.gpio69 = GPIO_MODE_GPIO,
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.gpio70 = GPIO_MODE_NATIVE,
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.gpio71 = GPIO_MODE_NATIVE,
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.gpio72 = GPIO_MODE_GPIO,
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.gpio73 = GPIO_MODE_NATIVE,
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.gpio74 = GPIO_MODE_NATIVE,
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.gpio75 = GPIO_MODE_NATIVE,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_direction = {
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.gpio68 = GPIO_DIR_INPUT,
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.gpio69 = GPIO_DIR_INPUT,
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.gpio72 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_level = {
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};
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static const struct pch_gpio_set3 pch_gpio_set3_reset = {
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};
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const struct pch_gpio_map mainboard_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.blink = &pch_gpio_set1_blink,
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.invert = &pch_gpio_set1_invert,
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.reset = &pch_gpio_set1_reset,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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.reset = &pch_gpio_set2_reset,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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.reset = &pch_gpio_set3_reset,
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},
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};
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@ -0,0 +1,42 @@
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/*
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* This file is part of the coreboot project.
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*
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||||
* Copyright (C) 2019 Angel Pons <th3fanbus@gmail.com>
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*
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||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
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|
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#include <device/azalia_device.h>
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const u32 cim_verb_data[] = {
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0x10ec0887, /* Realtek ALC887 */
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0x1458a002, /* Subsystem ID */
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15, /* Number of 4 dword sets */
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AZALIA_SUBVENDOR(2, 0x1458a002),
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AZALIA_PIN_CFG(2, 0x11, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x12, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x14, 0x01014410),
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AZALIA_PIN_CFG(2, 0x15, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x16, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x17, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x18, 0x01a19c50),
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AZALIA_PIN_CFG(2, 0x19, 0x02a19c60),
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AZALIA_PIN_CFG(2, 0x1a, 0x0181345f),
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AZALIA_PIN_CFG(2, 0x1b, 0x02214c20),
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AZALIA_PIN_CFG(2, 0x1c, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x1d, 0x4004c601),
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AZALIA_PIN_CFG(2, 0x1e, 0x411111f0),
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AZALIA_PIN_CFG(2, 0x1f, 0x411111f0),
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};
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const u32 pc_beep_verbs[0] = {};
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AZALIA_ARRAY_SIZES;
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