just to get us back where we were.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1151 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
430111b9d1
commit
11dbdf5d78
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@ -11,6 +11,8 @@
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/via/vt8601/raminit.h"
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/*
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*/
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void udelay(int usecs) {
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int i;
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for(i = 0; i < usecs; i++)
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@ -43,21 +45,24 @@ static inline int spd_read_byte(unsigned device, unsigned address)
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#include "northbridge/via/vt8601/raminit.c"
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#include "sdram/generic_sdram.c"
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/*
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#include "sdram/generic_sdram.c"
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*/
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static void main(void)
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{
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struct mem_controller cpu[1];
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// init_timer();
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/* init_timer();*/
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uart_init();
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console_init();
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enable_smbus();
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/*
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memreset_setup();
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// sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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this is way more generic than we need.
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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*/
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sdram_set_registers((const struct mem_controller *) 0);
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/* Check all of memory */
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@ -33,18 +33,6 @@ it with the version available from LANL.
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* 5/19/03 by SONE Takeshi <ts1@tsn.or.jp>
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*/
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// Set to 1 if your DIMMs are PC133
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// Note that I'm assuming CPU's FSB frequency is 133MHz. If your CPU runs
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// at another bus speed, you might need to change some of register values.
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#ifndef DIMM_PC133
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#define DIMM_PC133 0
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#endif
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// Set to 1 if your DIMMs are CL=2
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#ifndef DIMM_CL2
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#define DIMM_CL2 0
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#endif
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/* Stable ~1 usec delay by hitting unused ISA port. */
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#define UDELAY(x) movl $x,%ecx; 9: outb %al,$0x81; loop 9b
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@ -310,7 +298,246 @@ msg_bytes:
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.previous
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#endif
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/* this is an early hack. We're going to just try to get memory
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* working as it was before. I need help for SPD! RGM
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*/
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// Set to 1 if your DIMMs are PC133
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// Note that I'm assuming CPU's FSB frequency is 133MHz. If your CPU runs
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// at another bus speed, you might need to change some of register values.
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#ifndef DIMM_PC133
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#define DIMM_PC133 0
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#endif
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// Set to 1 if your DIMMs are CL=2
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#ifndef DIMM_CL2
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#define DIMM_CL2 0
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#endif
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/* Stable ~1 usec delay by hitting unused ISA port. */
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#define UDELAY(x) movl $x,%ecx; 9: outb %al,$0x81; loop 9b
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void dimms_read(unsigned long x) {
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unsigned long eax;
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volatile unsigned long y;
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eax = x;
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for(; eax < 0x60000000; eax += 0x10000000)
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y = * (volatile unsigned long *) eax;
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}
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void dimms_write(int x) {
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unsigned long eax = x;
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for(; eax < 0x60000000; eax += 0x10000000)
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*(volatile unsigned long *) eax = 0;
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}
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static void sdram_set_registers(const struct mem_controller *ctrl) {
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static const uint16_t raminit_ma_reg_table[] = {
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/* Values for MA type register to try */
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0x0000, 0x8088, 0xe0ee,
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0xffff // end mark
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};
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device_t north = 0;
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uint8_t c, r;
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print_err("vt8601 init starting\n");
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north = pci_locate_device(PCI_ID(0x1106, 0x8601), north);
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print_err_hex32(north);
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print_err(" is the north\n");
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// memory clk enable. We are not using ECC
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pci_write_config8(north,0x78, 0x01);
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// dram control, see the book.
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#if DIMM_PC133
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pci_write_config8(north,0x68, 0x52);
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#else
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pci_write_config8(north,0x68, 0x42);
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#endif
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// dram control, see the book.
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pci_write_config8(north,0x6B, 0x0c);
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// Initial setting, 256MB in each bank, will be rewritten later.
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pci_write_config8(north,0x5A, 0x20);
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pci_write_config8(north,0x5B, 0x40);
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pci_write_config8(north,0x5C, 0x60);
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pci_write_config8(north,0x5D, 0x80);
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pci_write_config8(north,0x5E, 0xA0);
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pci_write_config8(north,0x5F, 0xC0);
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// It seems we have to take care of these 2 registers as if
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// they are bank 6 and 7.
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pci_write_config8(north,0x56, 0xC0);
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pci_write_config8(north,0x57, 0xC0);
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// SDRAM in all banks
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pci_write_config8(north,0x60, 0x3F);
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// DRAM timing. I'm suspicious of this
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// This is for all banks, 64 is 0,1. 65 is 2,3. 66 is 4,5.
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// ras precharge 4T, RAS pulse 5T
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// cas2 is 0xd6, cas3 is 0xe6
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// we're also backing off write pulse width to 2T, so result is 0xee
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#if DIMM_CL2
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pci_write_config8(north,0x64, 0xd4);
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pci_write_config8(north,0x65, 0xd4);
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pci_write_config8(north,0x66, 0xd4);
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#else // CL=3
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pci_write_config8(north,0x64, 0xe4);
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pci_write_config8(north,0x65, 0xe4);
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pci_write_config8(north,0x66, 0xe4);
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#endif
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// dram frequency select.
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// enable 4K pages for 64M dram.
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#if DIMM_PC133
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pci_write_config8(north,0x69, 0x3c);
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#else
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pci_write_config8(north,0x69, 0xac);
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#endif
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// refresh counter, disabled.
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pci_write_config8(north,0x6A, 0x00);
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// clkenable configuration. kevinh FIXME - add precharge
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pci_write_config8(north,0x6C, 0x00);
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// dram read latch delay of 1 ns, MD drive 8 mA,
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// high drive strength on MA[2: 13], we#, cas#, ras#
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// As per Cindy Lee, set to 0x37, not 0x57
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pci_write_config8(north,0x6D, 0x7f);
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/* Initialize all banks at once */
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/* begin to initialize*/
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// I forget why we need this, but we do
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dimms_write(0xa55a5aa5);
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/* set NOP*/
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pci_write_config8(north,0x6C, 0x01);
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/* wait 200us*/
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// You need to do the memory reference. That causes the nop cycle.
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dimms_read(0);
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udelay(400);
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/* set precharge */
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pci_write_config8(north,0x6C, 0x02);
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/* dummy reads*/
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dimms_read(0);
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udelay(200);
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/* set CBR*/
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pci_write_config8(north,0x6C, 0x04);
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/* do 8 reads and wait >100us between each - from via*/
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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dimms_read(0);
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udelay(200);
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/* set MRS*/
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pci_write_config8(north,0x6c, 0x03);
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#if DIMM_CL2
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dimms_read(0x150);
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#else // CL=3
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dimms_read(0x1d0);
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#endif
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udelay(200);
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/* set to normal mode */
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pci_write_config8(north,0x6C, 0x08);
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dimms_write(0x55aa55aa);
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dimms_read(0);
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udelay(200);
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// Set the refresh rate.
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#if DIMM_PC133
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pci_write_config8(north,0x6A, 0x86);
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#else
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pci_write_config8(north,0x6A, 0x65);
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#endif
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// enable multi-page open
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pci_write_config8(north,0x6B, 0x0d);
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/* Begin auto-detection
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* Find the first bank with DIMM equipped. */
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/* Maximum possible memory in bank 0, none in other banks.
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* Starting from bank 0, we's fill 0 in these registers
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* until memory is found. */
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pci_write_config8(north,0x5A, 0xff);
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pci_write_config8(north,0x5B, 0xff);
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pci_write_config8(north,0x5C, 0xff);
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pci_write_config8(north,0x5D, 0xff);
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pci_write_config8(north,0x5E, 0xff);
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pci_write_config8(north,0x5F, 0xff);
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pci_write_config8(north,0x56, 0xff);
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pci_write_config8(north,0x57, 0xff);
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/* this code is broken ... ignores 56, 57 */
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for(c = 0x5a; c < 0x60; c++) {
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/* Write different values to 0 and 8, then read from 0.
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* If values of address 0 match, we have something there. */
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*(volatile unsigned long *) 0 = 0x12345678;
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/* LEAVE THIS HERE. IT IS ESSENTIAL. OTHERWISE BUFFERING
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* WILL FOOL YOU!
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*/
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*(volatile unsigned long *) 8 = 0x87654321;
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if (*(volatile unsigned long *) 0 != 0x12345678) {
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/* No memory in this bank. Tell it to the bridge. */
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pci_write_config8(north,c, 0);
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} else {
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uint8_t best = 0;
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/* Detect MA mapping type of the first bank. */
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for(r = 0; r < 3; r++) {
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volatile unsigned long esi = 0;
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volatile unsigned long eax = 0;
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pci_write_config8(north,0x58, raminit_ma_reg_table[r]);
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* (volatile unsigned long *) eax = 0;
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// Write to addresses with only one address bit
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// on, from 0x80000000 to 0x00000008 (lower 3 bits
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// are ignored, assuming 64-bit bus). Then what
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// is read at address 0 is the value written to
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// the lowest address where it gets
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// wrap-around. That address is either the size of
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// the bank, or a missing bit due to incorrect MA
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// mapping.
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eax = 0x80000000;
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while (eax != 4) {
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eax = * (volatile unsigned long *) eax;
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eax >>= 1;
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}
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eax = 0;
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/* oh boy ... what is this.
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movl 0, %eax
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cmpl %eax, %esi
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jnc 3f
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*/
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if (eax < esi) { /* ??*/
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// This is the current best MA mapping.
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// Save the address and its MA mapping value.
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best = r;
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esi = eax;
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}
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}
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pci_write_config8(north,0x58, raminit_ma_reg_table[best]);
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print_err("enabled first bank of ram ...\n");
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}
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}
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print_err("vt8601 done\n");
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}
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static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
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