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soc/mediatek/mt8186: Enable thermal hardware reset 

Under the current watchdog setting, the system will not reboot when the
temperature is too high. To enable thermal hardware reset, we need to
enable thermal control request and set it to reboot mode.

Note that because thermal throttle (by lowering cpu frequency) is
currently enabled, the thermal hardware reset shouldn't be triggered
under normal circumstances.

This feature is only for new hardware structure for thermal. Therefore,
we only need to apply it on MT8192/MT8195/MT8186.

This setting is based on thermal and watchdog section of MT8186
Function Specification.

BUG=none
TEST=emerge-corsola coreboot
TEST=thermal hardware reset is working.

Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: Id2ed55e6d4f4eec450bf7c849f726a389eeb6694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64659
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Runyang Chen 2022-05-10 20:13:50 +08:00 committed by Martin L Roth
parent 404188f80e
commit 11e2e36c06
2 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/mediatek/common/include/soc/wdt.h
View File

@ -16,7 +16,8 @@ struct mtk_wdt_regs {
u32 wdt_swsysrst;
u32 reserved0[5];
u32 wdt_req_mode;
u32 reserved1[3];
u32 wdt_req_irq_en;
u32 reserved1[2];
u32 wdt_debug_ctrl;
};

8
src/soc/mediatek/mt8186/wdt.c
View File

@ -11,16 +11,24 @@
#define MTK_WDT_CLR_STATUS_VAL 0x22
#define MTK_WDT_REQ_MOD_KEY_VAL 0x33
#define MTK_WDT_REQ_IRQ_KEY_VAL 0x44
DEFINE_BITFIELD(MTK_WDT_CLR_STATUS, 31, 24)
DEFINE_BITFIELD(MTK_WDT_REQ_MOD_KEY, 31, 24)
DEFINE_BITFIELD(MTK_WDT_REQ_IRQ_KEY, 31, 24)
DEFINE_BIT(MTK_WDT_SPM_THERMAL_EN, 0)
DEFINE_BIT(MTK_WDT_THERMAL_EN, 18)
DEFINE_BIT(MTK_WDT_THERMAL_IRQ, 18)
void mtk_wdt_preinit(void)
{
SET32_BITFIELDS(&mtk_wdt->wdt_req_mode,
MTK_WDT_SPM_THERMAL_EN, 0,
MTK_WDT_THERMAL_EN, 1,
MTK_WDT_REQ_MOD_KEY, MTK_WDT_REQ_MOD_KEY_VAL);
SET32_BITFIELDS(&mtk_wdt->wdt_req_irq_en,
MTK_WDT_THERMAL_IRQ, 0,
MTK_WDT_REQ_IRQ_KEY, MTK_WDT_REQ_IRQ_KEY_VAL);
}
void mtk_wdt_clr_status(void)