mediatek/mt8173: Add RTC driver
BUG=none TEST=emerge-oak coreboot BRANCH=none Change-Id: I03740ce1afeb8607891fff61110a40dd98b80bdc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9b0cc22cb9e2010e28e854d9984c11149a71ae0b Original-Change-Id: I6d6482a75cc40ed6183ee115d5d866257afa24af Original-Signed-off-by: Tianping Fang <tianping.fang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292676 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/12616 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Tianping Fang
Patrick Georgi
parent
d95a463e49
commit
11f4a297c0
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@ -26,7 +26,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += uart.c
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endif
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bootblock-y += gpio.c gpio_init.c pmic_wrap.c mt6391.c
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bootblock-y += wdt.c
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bootblock-y += wdt.c rtc.c
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bootblock-y += mmu_operations.c
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################################################################################
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@ -17,6 +17,7 @@
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#include <soc/mmu_operations.h>
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#include <soc/mt6391.h>
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#include <soc/pll.h>
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#include <soc/rtc.h>
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#include <soc/wdt.h>
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void bootblock_soc_init(void)
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@ -33,4 +34,6 @@ void bootblock_soc_init(void)
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/* init watch dog, will disable AP watch dog */
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mtk_wdt_init();
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rtc_boot();
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}
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@ -0,0 +1,184 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SOC_MEDIATEK_MT8173_RTC_H
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#define SOC_MEDIATEK_MT8173_RTC_H
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#include <stdint.h>
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#include "mt6391.h"
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/*
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* Default values for RTC initialization
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* Year (YEA) : 1970 ~ 2037
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* Month (MTH) : 1 ~ 12
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* Day of Month (DOM): 1 ~ 31
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*/
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enum {
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RTC_DEFAULT_YEA = 2010,
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RTC_DEFAULT_MTH = 1,
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RTC_DEFAULT_DOM = 1,
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RTC_DEFAULT_DOW = 5
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};
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enum {
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RTC_2SEC_REBOOT_ENABLE = 1,
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RTC_2SEC_MODE = 2
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};
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/* RTC registers */
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enum {
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RTC_BBPU = 0xE000,
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RTC_IRQ_STA = 0xE002,
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RTC_IRQ_EN = 0xE004,
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RTC_CII_EN = 0xE006
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};
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enum {
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RTC_TC_SEC = 0xE00A,
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RTC_TC_MIN = 0xE00C,
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RTC_TC_HOU = 0xE00E,
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RTC_TC_DOM = 0xE010,
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RTC_TC_DOW = 0xE012,
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RTC_TC_MTH = 0xE014,
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RTC_TC_YEA = 0xE016
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};
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enum {
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RTC_AL_SEC = 0xE018,
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RTC_AL_MIN = 0xE01A,
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RTC_AL_HOU = 0xE01C,
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RTC_AL_DOM = 0xE01E,
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RTC_AL_DOW = 0xE020,
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RTC_AL_MTH = 0xE022,
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RTC_AL_YEA = 0xE024,
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RTC_AL_MASK = 0xE008
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};
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enum {
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RTC_OSC32CON = 0xE026,
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RTC_CON = 0xE03E,
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RTC_WRTGR = 0xE03C
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};
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enum {
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RTC_POWERKEY1 = 0xE028,
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RTC_POWERKEY2 = 0xE02A
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};
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enum {
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RTC_PDN1 = 0xE02C,
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RTC_PDN2 = 0xE02E,
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RTC_SPAR0 = 0xE030,
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RTC_SPAR1 = 0xE032,
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RTC_PROT = 0xE036,
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RTC_DIFF = 0xE038,
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RTC_CALI = 0xE03A
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};
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enum {
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RTC_OSC32CON_UNLOCK1 = 0x1A57,
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RTC_OSC32CON_UNLOCK2 = 0x2B68
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};
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enum {
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RTC_PROT_UNLOCK1 = 0x586A,
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RTC_PROT_UNLOCK2 = 0x9136
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};
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enum {
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RTC_BBPU_PWREN = 1U << 0,
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RTC_BBPU_BBPU = 1U << 2,
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RTC_BBPU_AUTO = 1U << 3,
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RTC_BBPU_CLRPKY = 1U << 4,
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RTC_BBPU_RELOAD = 1U << 5,
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RTC_BBPU_CBUSY = 1U << 6,
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RTC_CBUSY_TIMEOUT_US = 800
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};
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enum {
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RTC_BBPU_KEY = 0x43 << 8
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};
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enum {
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RTC_IRQ_STA_AL = 1U << 0,
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RTC_IRQ_STA_TC = 1U << 1,
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RTC_IRQ_STA_LP = 1U << 3
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};
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enum {
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RTC_IRQ_EN_AL = 1U << 0,
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RTC_IRQ_EN_TC = 1U << 1,
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RTC_IRQ_EN_ONESHOT = 1U << 2,
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RTC_IRQ_EN_LP = 1U << 3,
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RTC_IRQ_EN_ONESHOT_AL = RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL
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};
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enum {
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RTC_OSC32CON_AMPEN = 1U << 8,
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RTC_OSC32CON_LNBUFEN = 1U << 11
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};
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enum {
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RTC_POWERKEY1_KEY = 0xa357,
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RTC_POWERKEY2_KEY = 0x67d2
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};
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enum {
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RTC_CON_LPEN = 1U << 2,
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RTC_CON_LPRST = 1U << 3,
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RTC_CON_CDBO = 1U << 4,
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RTC_CON_F32KOB = 1U << 5,
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RTC_CON_GPO = 1U << 6,
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RTC_CON_GOE = 1U << 7,
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RTC_CON_GSR = 1U << 8,
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RTC_CON_GSMT = 1U << 9,
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RTC_CON_GPEN = 1U << 10,
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RTC_CON_GPU = 1U << 11,
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RTC_CON_GE4 = 1U << 12,
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RTC_CON_GE8 = 1U << 13,
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RTC_CON_GPI = 1U << 14,
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RTC_CON_LPSTA_RAW = 1U << 15
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};
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enum {
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RTC_CALI_BBPU_2SEC_EN = 1U << 8,
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RTC_CALI_BBPU_2SEC_MODE_SHIFT = 9,
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RTC_CALI_BBPU_2SEC_MODE_MSK = 3U << RTC_CALI_BBPU_2SEC_MODE_SHIFT,
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RTC_CALI_BBPU_2SEC_STAT = 1U << 11
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};
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enum {
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RTC_SPAR0_32K_LESS = 1U << 6
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};
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enum {
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RTC_MIN_YEAR = 1968,
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RTC_BASE_YEAR = 1900,
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RTC_MIN_YEAR_OFFSET = RTC_MIN_YEAR - RTC_BASE_YEAR,
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RTC_NUM_YEARS = 128
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};
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enum {
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RTC_STATE_REBOOT = 0,
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RTC_STATE_RECOVER = 1,
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RTC_STATE_INIT = 2
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};
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void rtc_boot(void);
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#endif /* SOC_MEDIATEK_MT8173_RTC_H */
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@ -0,0 +1,317 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2015 MediaTek Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <assert.h>
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#include <bcd.h>
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#include <console/console.h>
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#include <delay.h>
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#include <rtc.h>
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#include <timer.h>
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#include <soc/mt6391.h>
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#include <soc/pmic_wrap.h>
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#include <soc/rtc.h>
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#define RTC_GPIO_USER_MASK ((1 << 13) - (1 << 8))
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/* ensure rtc write success */
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static inline int rtc_busy_wait(void)
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{
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struct stopwatch sw;
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u16 bbpu;
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stopwatch_init_usecs_expire(&sw, RTC_CBUSY_TIMEOUT_US);
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do {
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pwrap_read(RTC_BBPU, &bbpu);
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/* Time > 1sec, time out and set recovery mode enable.*/
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if (stopwatch_expired(&sw)) {
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printk(BIOS_INFO, "[RTC] BBPU CBUSY time out !!\n");
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return 0;
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}
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} while (bbpu & RTC_BBPU_CBUSY);
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return 1;
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}
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static int write_trigger(void)
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{
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pwrap_write(RTC_WRTGR, 1);
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return rtc_busy_wait();
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}
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/* unlock rtc write interface */
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static int writeif_unlock(void)
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{
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pwrap_write(RTC_PROT, RTC_PROT_UNLOCK1);
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if (!write_trigger())
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return 0;
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pwrap_write(RTC_PROT, RTC_PROT_UNLOCK2);
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if (!write_trigger())
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return 0;
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return 1;
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}
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/* set rtc time */
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int rtc_set(const struct rtc_time *time)
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{
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return -1;
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}
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/* get rtc time */
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int rtc_get(struct rtc_time *time)
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{
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u16 value;
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pwrap_read(RTC_TC_SEC, &value);
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time->sec = value;
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pwrap_read(RTC_TC_MIN, &value);
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time->min = value;
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pwrap_read(RTC_TC_HOU, &value);
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time->hour = value;
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pwrap_read(RTC_TC_DOM, &value);
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time->mday = value;
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pwrap_read(RTC_TC_MTH, &value);
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time->mon = value;
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pwrap_read(RTC_TC_YEA, &value);
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time->year = (value + RTC_MIN_YEAR_OFFSET) % 100;
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return 0;
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}
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/* set rtc xosc setting */
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static void rtc_xosc_write(u16 val)
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{
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pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK1);
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udelay(200);
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pwrap_write(RTC_OSC32CON, RTC_OSC32CON_UNLOCK2);
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udelay(200);
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pwrap_write(RTC_OSC32CON, val);
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udelay(200);
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mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
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write_trigger();
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}
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/* initialize rtc related registers */
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static int rtc_reg_init(void)
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{
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u16 irqsta;
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pwrap_write(RTC_IRQ_EN, 0);
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pwrap_write(RTC_CII_EN, 0);
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pwrap_write(RTC_AL_MASK, 0);
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pwrap_write(RTC_AL_YEA, 1970 - RTC_MIN_YEAR);
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pwrap_write(RTC_AL_MTH, 1);
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pwrap_write(RTC_AL_DOM, 1);
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pwrap_write(RTC_AL_DOW, 4);
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pwrap_write(RTC_AL_HOU, 0);
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pwrap_write(RTC_AL_MIN, 0);
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pwrap_write(RTC_AL_SEC, 0);
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pwrap_write(RTC_DIFF, 0);
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pwrap_write(RTC_CALI, 0);
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if (!write_trigger())
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return 0;
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pwrap_read(RTC_IRQ_STA, &irqsta); /* read clear */
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/* init time counters after resetting RTC_DIFF and RTC_CALI */
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pwrap_write(RTC_TC_YEA, RTC_DEFAULT_YEA - RTC_MIN_YEAR);
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pwrap_write(RTC_TC_MTH, RTC_DEFAULT_MTH);
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pwrap_write(RTC_TC_DOM, RTC_DEFAULT_DOM);
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pwrap_write(RTC_TC_DOW, RTC_DEFAULT_DOW);
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pwrap_write(RTC_TC_HOU, 0);
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pwrap_write(RTC_TC_MIN, 0);
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pwrap_write(RTC_TC_SEC, 0);
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return write_trigger();
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}
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/* initialize rtc related gpio */
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static int rtc_gpio_init(void)
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{
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u16 con;
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mt6391_gpio_set_pull(3, MT6391_GPIO_PULL_DISABLE,
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MT6391_GPIO_PULL_DOWN); /* RTC_32K1V8 */
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/* Export 32K clock RTC_32K2V8 */
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pwrap_read(RTC_CON, &con);
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con &= (RTC_CON_LPSTA_RAW | RTC_CON_LPRST | RTC_CON_LPEN);
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con |= (RTC_CON_GPEN | RTC_CON_GOE);
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con &= ~(RTC_CON_F32KOB);
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pwrap_write(RTC_CON, con);
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return write_trigger();
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}
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/* set xosc mode */
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static void rtc_osc_init(void)
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{
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u16 con;
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/* enable 32K export */
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rtc_gpio_init();
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pwrap_write(PMIC_RG_TOP_CKTST2, 0x0);
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pwrap_read(RTC_OSC32CON, &con);
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if ((con & 0x1f) != 0x0) /* check XOSCCALI */
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rtc_xosc_write(0x3);
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}
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/* low power detect setting */
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static int rtc_lpd_init(void)
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{
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mt6391_write(RTC_CON, RTC_CON_LPEN, RTC_CON_LPRST, 0);
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if (!write_trigger())
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return 0;
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mt6391_write(RTC_CON, RTC_CON_LPRST, 0, 0);
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if (!write_trigger())
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return 0;
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mt6391_write(RTC_CON, 0, RTC_CON_LPRST, 0);
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if (!write_trigger())
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return 0;
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return 1;
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}
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/* rtc init check */
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static int rtc_init(u8 recover)
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{
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printk(BIOS_INFO, "[RTC] %s recovery: %d\n", __func__, recover);
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if (!writeif_unlock())
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return 0;
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if (!rtc_gpio_init())
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return 0;
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/* Use SW to detect 32K mode instead of HW */
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if (recover)
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mt6391_write(PMIC_RG_CHRSTATUS, 0x4, 0x1, 9);
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rtc_xosc_write(0x3);
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if (recover)
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mdelay(1000);
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/* write powerkeys */
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pwrap_write(RTC_POWERKEY1, RTC_POWERKEY1_KEY);
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pwrap_write(RTC_POWERKEY2, RTC_POWERKEY2_KEY);
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if (!write_trigger())
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return 0;
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if (recover)
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mt6391_write(PMIC_RG_CHRSTATUS, 0, 0x4, 9);
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rtc_xosc_write(0);
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if (!rtc_reg_init())
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return 0;
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if (!rtc_lpd_init())
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return 0;
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return 1;
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}
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/* enable rtc bbpu */
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static void rtc_bbpu_power_on(void)
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{
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u16 bbpu;
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int ret;
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/* pull PWRBB high */
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bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_BBPU | RTC_BBPU_PWREN;
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pwrap_write(RTC_BBPU, bbpu);
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ret = write_trigger();
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printk(BIOS_INFO, "[RTC] %s write_trigger=%d\n", __func__, ret);
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/* enable DCXO to transform external 32KHz clock to 26MHz clock
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directly sent to SoC */
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mt6391_write(PMIC_RG_DCXO_FORCE_MODE1, BIT(11), 0, 0);
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mt6391_write(PMIC_RG_DCXO_POR2_CON3,
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BIT(8) | BIT(9) | BIT(10) | BIT(11), 0, 0);
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mt6391_write(PMIC_RG_DCXO_CON2,
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BIT(1) | BIT(3) | BIT(5) | BIT(6), 0, 0);
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pwrap_read(RTC_BBPU, &bbpu);
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printk(BIOS_INFO, "[RTC] %s done BBPU=%#x\n", __func__, bbpu);
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/* detect hw clock done,close RG_RTC_75K_PDN for low power setting. */
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mt6391_write(PMIC_RG_TOP_CKPDN2, 0x1, 0, 14);
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}
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static u8 rtc_check_state(void)
|
||||
{
|
||||
u16 con;
|
||||
u16 pwrky1;
|
||||
u16 pwrky2;
|
||||
|
||||
pwrap_read(RTC_CON, &con);
|
||||
pwrap_read(RTC_POWERKEY1, &pwrky1);
|
||||
pwrap_read(RTC_POWERKEY2, &pwrky2);
|
||||
|
||||
if (con & RTC_CON_LPSTA_RAW)
|
||||
return RTC_STATE_INIT;
|
||||
|
||||
if (!rtc_busy_wait())
|
||||
return RTC_STATE_RECOVER;
|
||||
|
||||
if (!writeif_unlock())
|
||||
return RTC_STATE_RECOVER;
|
||||
|
||||
if (pwrky1 != RTC_POWERKEY1_KEY || pwrky2 != RTC_POWERKEY2_KEY)
|
||||
return RTC_STATE_INIT;
|
||||
else
|
||||
return RTC_STATE_REBOOT;
|
||||
}
|
||||
|
||||
/* the rtc boot flow entry */
|
||||
void rtc_boot(void)
|
||||
{
|
||||
u16 bbpu;
|
||||
u16 con;
|
||||
u16 irqsta;
|
||||
|
||||
pwrap_write(PMIC_RG_TOP_CKPDN, 0);
|
||||
pwrap_write(PMIC_RG_TOP_CKPDN2, 0);
|
||||
|
||||
switch (rtc_check_state()) {
|
||||
case RTC_STATE_REBOOT:
|
||||
mt6391_write(RTC_BBPU, RTC_BBPU_KEY | RTC_BBPU_RELOAD, 0, 0);
|
||||
write_trigger();
|
||||
rtc_osc_init();
|
||||
break;
|
||||
case RTC_STATE_RECOVER:
|
||||
rtc_init(1);
|
||||
break;
|
||||
case RTC_STATE_INIT:
|
||||
default:
|
||||
if (!rtc_init(0))
|
||||
rtc_init(1);
|
||||
break;
|
||||
}
|
||||
|
||||
pwrap_read(RTC_IRQ_STA, &irqsta); /* Read clear */
|
||||
pwrap_read(RTC_BBPU, &bbpu);
|
||||
pwrap_read(RTC_CON, &con);
|
||||
|
||||
printk(BIOS_INFO, "[RTC] irqsta = %x", irqsta);
|
||||
printk(BIOS_INFO, " bbpu = %#x, con = %#x\n", bbpu, con);
|
||||
rtc_bbpu_power_on();
|
||||
}
|
||||
Loading…
Reference in New Issue