soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNVi

Add CNVi GPE in _PRW for wake on WLAN from S3

Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Hannah Williams 2017-11-21 12:11:30 -08:00 committed by Martin Roth
parent cbae0cc931
commit 11f7dc87b2
3 changed files with 37 additions and 0 deletions

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@ -0,0 +1,30 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* CNVi Controller 0:C.0 */
Device (CNVI) {
Name(_ADR, 0x000C0000)
Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */
Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 })
Method (_STA, 0)
{
Return (0xF)
}
}

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@ -56,4 +56,10 @@ Scope (\_SB)
/* SGX */
#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
#include <soc/intel/common/acpi/sgx.asl>
/* CNVi */
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#include "cnvi.asl"
#endif
#endif

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@ -33,6 +33,7 @@
#define GPE0A_GPIO_TIER1_SCI_STS 15
#define GPE0A_SMB_WAK_STS 16
#define GPE0A_SATA_PME_STS 17
#define GPE0A_CNVI_PME_STS 18
/* Group DW0 is reserved in Apollolake */