soc/intel/apollolake/acpi/cnvi.asl: Add _PRW for CNVi
Add CNVi GPE in _PRW for wake on WLAN from S3 Change-Id: I682c76b9c5c524face7b540ecb185a3d7b4b2da3 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* CNVi Controller 0:C.0 */
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Device (CNVI) {
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Name(_ADR, 0x000C0000)
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Name (_S3D, 3) /* D3 supported in S3 */
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Name (_S0W, 3) /* D3 can wake device in S0 */
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Name (_S3W, 3) /* D3 can wake system from S3 */
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Name (_PRW, Package() { GPE0A_CNVI_PME_STS, 3 })
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Method (_STA, 0)
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{
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Return (0xF)
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}
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}
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@ -56,4 +56,10 @@ Scope (\_SB)
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/* SGX */
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#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
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#include <soc/intel/common/acpi/sgx.asl>
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/* CNVi */
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#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
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#include "cnvi.asl"
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#endif
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#endif
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@ -33,6 +33,7 @@
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#define GPE0A_GPIO_TIER1_SCI_STS 15
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#define GPE0A_SMB_WAK_STS 16
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#define GPE0A_SATA_PME_STS 17
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#define GPE0A_CNVI_PME_STS 18
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/* Group DW0 is reserved in Apollolake */
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