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mb/google/dedede/var/bugzzy: Configure USB ports 

Override USB port configurations based on the latest bugzzy schematics.

BUG=b:192521391
BRANCH=None
TEST=Built test coreboot image

Change-Id: I4368946f4175f4f065a3483dc7ca6068c6de3123
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Seunghwan Kim 2021-08-24 14:07:03 +09:00 committed by Felix Held
parent 58966086cd
commit 11f966df23
1 changed files with 51 additions and 1 deletions
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52
src/mainboard/google/dedede/variants/bugzzy/overridetree.cb
View File

@ -1,8 +1,35 @@
chip soc/intel/jasperlake chip soc/intel/jasperlake
# USB Port Configuration # USB Port Configuration
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_28P15MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C Port C0
register "usb2_ports[1]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_16P9MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_39P35MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-C Port C1
register "usb2_ports[2]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_bias = USB2_BIAS_11P25MV,
.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port A0
register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_EMPTY"
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |
@ -45,7 +72,30 @@ chip soc/intel/jasperlake
}, },
}" }"
device domain 0 on device domain 0 on
device pci 14.0 on end device pci 14.0 on
chip drivers/usb/acpi
device usb 0.0 on
chip drivers/usb/acpi
register "desc" = ""UFCamera""
register "type" = "UPC_TYPE_INTERNAL"
register "has_power_resource" = "1"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D13)"
register "enable_delay_ms" = "20"
device usb 2.5 on end
end
chip drivers/usb/acpi
register "desc" = ""LTE""
register "type" = "UPC_TYPE_INTERNAL"
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
register "reset_off_delay_ms" = "20"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)"
register "enable_delay_ms" = "20"
device usb 3.3 on end
end
end
end
end # USB xHCI
device pci 15.0 on end device pci 15.0 on end
device pci 15.2 on end device pci 15.2 on end
device pci 1c.7 on end device pci 1c.7 on end