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soc/amd/common/block/cpu/noncar: add get_usable_physical_address_bits() 

In case the secure memory encryption is enabled, some of the upper
usable address bits of the host can't be used any more. Bits 11..6 in
CPUID_EBX_MEM_ENCRYPT indicate how many of the address bits are taken
away from the usable address bits in the case the secure memory
encryption is enabled.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia810b0984972216095da2ad8f9c19e37684f2a2e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75623
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2023-06-06 00:29:58 +02:00
parent b39e93e56f
commit 11ff753407
4 changed files with 24 additions and 0 deletions
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4
src/include/cpu/amd/cpuid.h
View File

@ -121,4 +121,8 @@
#define CPUID_EBX_THREADS_SHIFT 8 #define CPUID_EBX_THREADS_SHIFT 8
#define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT) #define CPUID_EBX_THREADS_MASK (0xff << CPUID_EBX_THREADS_SHIFT)
#define CPUID_EBX_MEM_ENCRYPT 0x8000001f
#define CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT 6
#define CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK (0x3f << CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT)
#endif /* CPU_AMD_CPUID_H */ #endif /* CPU_AMD_CPUID_H */

1
src/include/cpu/amd/mtrr.h
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@ -12,6 +12,7 @@
#define MTRR_WRITE_MEM (1 << 3) #define MTRR_WRITE_MEM (1 << 3)
#define SYSCFG_MSR 0xC0010010 #define SYSCFG_MSR 0xC0010010
#define SYSCFG_MSR_SMEE (1 << 23)
#define SYSCFG_MSR_TOM2WB (1 << 22) #define SYSCFG_MSR_TOM2WB (1 << 22)
#define SYSCFG_MSR_TOM2En (1 << 21) #define SYSCFG_MSR_TOM2En (1 << 21)
#define SYSCFG_MSR_MtrrVarDramEn (1 << 20) #define SYSCFG_MSR_MtrrVarDramEn (1 << 20)

18
src/soc/amd/common/block/cpu/noncar/cpu.c
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@ -1,9 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h> #include <amdblocks/cpu.h>
#include <arch/cpuid.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/amd/cpuid.h>
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <smbios.h> #include <smbios.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <types.h> #include <types.h>
@ -31,3 +34,18 @@ void set_cstate_io_addr(void)
cst_addr.lo = ACPI_CSTATE_CONTROL; cst_addr.lo = ACPI_CSTATE_CONTROL;
wrmsr(MSR_CSTATE_ADDRESS, cst_addr); wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
} }
static uint32_t get_smee_reserved_address_bits(void)
{
if (rdmsr(SYSCFG_MSR).raw & SYSCFG_MSR_SMEE)
return (cpuid_ebx(CPUID_EBX_MEM_ENCRYPT) &
CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_MASK) >>
CPUID_EBX_MEM_ENCRYPT_ADDR_BITS_SHIFT;
else
return 0;
}
uint32_t get_usable_physical_address_bits(void)
{
return cpu_phys_address_size() - get_smee_reserved_address_bits();
}

1
src/soc/amd/common/block/include/amdblocks/cpu.h
View File

@ -12,6 +12,7 @@ void early_cache_setup(void);
int get_cpu_count(void); int get_cpu_count(void);
unsigned int get_threads_per_core(void); unsigned int get_threads_per_core(void);
void set_cstate_io_addr(void); void set_cstate_io_addr(void);
uint32_t get_usable_physical_address_bits(void);
void write_resume_eip(void); void write_resume_eip(void);
union pstate_msr; /* proper definition is in soc/msr.h */ union pstate_msr; /* proper definition is in soc/msr.h */