soc/intel/tigerlake: Rename pch_init() code
Rename the pch_init function to bootblock_pch_init and romstage_pch_init according to the stage it is defined in. TEST=successfully built and booted TGLRVP Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com> Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
parent
85a4463976
commit
12016969c5
|
@ -25,7 +25,7 @@ void bootblock_soc_early_init(void)
|
||||||
void bootblock_soc_init(void)
|
void bootblock_soc_init(void)
|
||||||
{
|
{
|
||||||
report_platform_info();
|
report_platform_info();
|
||||||
pch_init();
|
bootblock_pch_init();
|
||||||
|
|
||||||
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
|
/* Programming TCO_BASE_ADDRESS and TCO Timer Halt */
|
||||||
tco_configure();
|
tco_configure();
|
||||||
|
|
|
@ -141,7 +141,7 @@ void pch_early_iorange_init(void)
|
||||||
pch_enable_lpc();
|
pch_enable_lpc();
|
||||||
}
|
}
|
||||||
|
|
||||||
void pch_init(void)
|
void bootblock_pch_init(void)
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
|
* Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT,
|
||||||
|
|
|
@ -8,7 +8,7 @@ void bootblock_cpu_init(void);
|
||||||
void bootblock_pch_early_init(void);
|
void bootblock_pch_early_init(void);
|
||||||
|
|
||||||
/* Bootblock post console init programming */
|
/* Bootblock post console init programming */
|
||||||
void pch_init(void);
|
void bootblock_pch_init(void);
|
||||||
void pch_early_iorange_init(void);
|
void pch_early_iorange_init(void);
|
||||||
void report_platform_info(void);
|
void report_platform_info(void);
|
||||||
|
|
||||||
|
|
|
@ -9,7 +9,7 @@
|
||||||
bool mainboard_get_dram_part_num(const char **part_num, size_t *len);
|
bool mainboard_get_dram_part_num(const char **part_num, size_t *len);
|
||||||
void mainboard_memory_init_params(FSPM_UPD *mupd);
|
void mainboard_memory_init_params(FSPM_UPD *mupd);
|
||||||
void systemagent_early_init(void);
|
void systemagent_early_init(void);
|
||||||
void pch_init(void);
|
void romstage_pch_init(void);
|
||||||
|
|
||||||
/* Board type */
|
/* Board type */
|
||||||
enum board_type {
|
enum board_type {
|
||||||
|
|
|
@ -3,7 +3,7 @@
|
||||||
#include <intelblocks/smbus.h>
|
#include <intelblocks/smbus.h>
|
||||||
#include <soc/romstage.h>
|
#include <soc/romstage.h>
|
||||||
|
|
||||||
void pch_init(void)
|
void romstage_pch_init(void)
|
||||||
{
|
{
|
||||||
/* Program SMBUS_BASE_ADDRESS and Enable it */
|
/* Program SMBUS_BASE_ADDRESS and Enable it */
|
||||||
smbus_common_init();
|
smbus_common_init();
|
||||||
|
|
|
@ -131,7 +131,7 @@ void mainboard_romstage_entry(void)
|
||||||
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
|
/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
|
||||||
systemagent_early_init();
|
systemagent_early_init();
|
||||||
/* Program PCH init */
|
/* Program PCH init */
|
||||||
pch_init();
|
romstage_pch_init();
|
||||||
/* initialize Heci interface */
|
/* initialize Heci interface */
|
||||||
heci_init(HECI1_BASE_ADDRESS);
|
heci_init(HECI1_BASE_ADDRESS);
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue