vboot: Select SoC-specific configuration for all Chrome OS boards

Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).

(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)

Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Julius Werner 2017-03-27 19:26:32 -07:00
parent 84b2978ed6
commit 1210b41283
12 changed files with 34 additions and 1 deletions

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@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_512
select BOOTBLOCK_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select SPI_FLASH_WINBOND
select CPU_IMGTEC_PISTACHIO
select COMMON_CBFS_SPI_WRAPPER

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@ -25,6 +25,9 @@ config NORTHBRIDGE_INTEL_HASWELL
if NORTHBRIDGE_INTEL_HASWELL
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config BOOTBLOCK_NORTHBRIDGE_INIT
string
default "northbridge/intel/haswell/bootblock.c"

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@ -32,6 +32,9 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
if NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_SANDYBRIDGE
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config USE_NATIVE_RAMINIT
bool "Use native raminit"
default y

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@ -29,6 +29,7 @@ config SOC_BROADCOM_CYGNUS
if SOC_BROADCOM_CYGNUS
config CHROMEOS
select VBOOT_STARTS_IN_BOOTBLOCK
select SEPARATE_VERSTAGE
select RETURN_FROM_VERSTAGE

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@ -39,6 +39,9 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/baytrail/bootblock/bootblock.c"

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@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_INTEL_FIRMWARE
select HAVE_SPI_CONSOLE_SUPPORT
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/braswell/bootblock/bootblock.c"

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@ -46,6 +46,9 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SPI_CONSOLE_SUPPORT
select CPU_INTEL_COMMON
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/broadwell/bootblock/cpu.c"

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@ -18,6 +18,8 @@ config SOC_NVIDIA_TEGRA210
if SOC_NVIDIA_TEGRA210
config CHROMEOS
select VBOOT_STARTS_IN_BOOTBLOCK
select SEPARATE_VERSTAGE
select VBOOT_OPROM_MATTERS
config MAINBOARD_DO_DSI_INIT

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@ -13,6 +13,7 @@ config SOC_QC_IPQ40XX
if SOC_QC_IPQ40XX
config CHROMEOS
select VBOOT_STARTS_IN_BOOTBLOCK
select RETURN_FROM_VERSTAGE
select SEPARATE_VERSTAGE
select VBOOT_VBNV_FLASH

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@ -12,6 +12,7 @@ config SOC_QC_IPQ806X
if SOC_QC_IPQ806X
config CHROMEOS
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_FLASH
select SEPARATE_VERSTAGE
select RETURN_FROM_VERSTAGE

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@ -10,3 +10,10 @@ config CPU_SAMSUNG_EXYNOS5250
select HAVE_HARD_RESET
bool
default n
if CPU_SAMSUNG_EXYNOS5250
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
endif

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@ -9,3 +9,10 @@ config CPU_SAMSUNG_EXYNOS5420
select RELOCATABLE_MODULES
bool
default n
if CPU_SAMSUNG_EXYNOS5420
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE
endif