mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard. Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit. Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio. TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation. Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload. Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Maxim Polyakov
Patrick Georgi
parent
03c60a5054
commit
1217af5e1a
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# ASRock H110M-DVS
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This page describes how to run coreboot on the [ASRock H110M-DVS].
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## Required proprietary blobs
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Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset.
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Intel company provides [Firmware Support Package (2.0)](../../Documentation/soc/intel/fsp/index.md)
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(intel FSP 2.0) to initialize this generation silicon. Please see this
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[document](../../Documentation/soc/intel/code_development_model/code_development_model.md).
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FSP Information:
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```eval_rst
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+-----------------------------+-------------------+-------------------+
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| FSP Project Name | Directory | Specification |
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+-----------------------------+-------------------+-------------------+
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| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 |
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| processors and chipsets | | |
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| (formerly Kaby Lake) | | |
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+-----------------------------+-------------------+-------------------+
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```
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Please take FSP from the directory `3rdparty/fsp/KabylakeFspBinPkg/` in
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the coreboot or download the latest version from [github][FSP github].
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You must use [Intel Binary Configuration Tool] BCT to set the following
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parameters in FSP.fd to initialize the PEG x16 port:
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```
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Peg0Enable = Enable
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Peg0MaxLinkSpeed = Gen3
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Peg0MaxLinkWidth = Auto
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```
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BCT creates Fsp_M.fd, Fsp_S.fd and Fsp_T.fd. These files are integrated
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into the coreboot image. If PEG port is not used, you can get these files
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without BTC:
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```bash
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# split FSP.fd
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python 3rdparty/fsp/Tools/SplitFspBin.py split -f 3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd
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```
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## Building coreboot
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The following steps set the default parameters for this board to build a
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fully working image:
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```bash
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make distclean
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touch .config
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./util/scripts/config --enable VENDOR_ASROCK
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./util/scripts/config --enable BOARD_ASROCK_H110M_DVS
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./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES
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./util/scripts/config --set-str CONFIG_FSP_M_FILE "/path/to/Fsp_M.fd"
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./util/scripts/config --set-str CONFIG_FSP_S_FILE "/path/to/Fsp_S.fd"
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./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx"
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make olddefconfig
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```
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However, it is strongly advised to use `make menuconfig` afterwards
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(or instead), so that you can see all of the settings.
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Use the following command to disable the serial console if debugging
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output is not required:
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```bash
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./util/scripts/config --disable CONSOLE_SERIAL
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```
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However, a more flexible method is to change the console log level from
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within an OS using `util/nvramtool`, or with the `nvramcui` payload.
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Now, run `make` to build the coreboot image.
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## Flashing coreboot
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### Internal programming
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The main SPI flash can be accessed using [flashrom]. By default, only
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the BIOS region of the flash is writable. If you wish to change any
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other region, such as the Management Engine or firmware descriptor, then
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an external programmer is required (unless you find a clever way around
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the flash protection). More information about this [here](../../Documentation/flash_tutorial/index.md).
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### External programming
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The flash chip is a 8 MiB socketed DIP-8 chip. Specifically, it's a
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Macronix MX25L6473E, whose datasheet can be found [here][MX25L6473E].
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The chip is located to the bottom right-hand side of the board. For
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a precise location, refer to section 1.3 (Motherboard Layout) of the
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[H110M-DVS manual], where the chip is labelled "64Mb BIOS". Take note of
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the chip's orientation, remove it from its socket, and flash it with
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an external programmer. For reference, the notch in the chip should be
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facing towards the bottom of the board.
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## Known issues
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- The VGA port doesn't work.
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- PEG x16 port training correctly runs only at link speed of 2.5GT/s(gen1).
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It takes more time to research the schematic of this board.
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- SuperIO GPIO pin is used to reset Realtek chip. However, since the
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Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network
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chip is in a reset state all the time.
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## Untested
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- parallel port
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- PS/2 keyboard
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- PS/2 mouse
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- EHCI debug
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- TPM
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- infrared module
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- chassis intrusion header
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- chassis speaker header
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## Working
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- integrated graphics init with libgfxinit (see [Known issues](#known-issues))
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- PCIe x1
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- PEG x16 Gen1 (see [Known issues](#known-issues))
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- SATA
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- USB
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- serial port
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- onboard audio
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- using `me_cleaner`
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- using `flashrom`
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## TODO
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- PEG x16 Gen3
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- NCT6791D GPIOs
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- onboard network (see [Known issues](#known-issues))
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- S3 suspend/resume
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- Wake-on-LAN
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- hardware monitor
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## Technology
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```eval_rst
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+------------------+--------------------------------------------------+
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| CPU | Intel Skylake/Kaby Lake (LGA1151) |
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+------------------+--------------------------------------------------+
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| PCH | Intel Sunrise Point H110 |
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+------------------+--------------------------------------------------+
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| Super I/O | Nuvoton NCT6791D |
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+------------------+--------------------------------------------------+
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| EC | None |
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+------------------+--------------------------------------------------+
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| Coprocessor | Intel Management Engine |
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+------------------+--------------------------------------------------+
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```
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[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
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[FSP github]: https://github.com/IntelFsp/FSP
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[Intel Binary Configuration Tool]: https://github.com/IntelFsp/BCT
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[MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2064Mb,%20v1.4.pdf
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[flashrom]: https://flashrom.org/Flashrom
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[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf
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@ -10,6 +10,7 @@ This section contains documentation about coreboot on specific mainboards.
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## ASRock
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- [H81M-HDS](asrock/h81m-hds.md)
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- [H110M-DVS](asrock/h110m-dvs.md)
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## Cavium
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if BOARD_ASROCK_H110M_DVS
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select INTEL_GMA_HAVE_VBT
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select INTEL_INT15
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select SOC_INTEL_KABYLAKE
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select SKYLAKE_SOC_PCH_H
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select MAINBOARD_USES_FSP2_0
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select GENERIC_SPD_BIN
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select SUPERIO_NUVOTON_NCT6791D
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select SUPERIO_NUVOTON_NCT6776_COM_A
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select REALTEK_8168_RESET
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select RT8168_SET_LED_MODE
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAINBOARD_DIR
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string
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default "asrock/h110m"
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config MAINBOARD_PART_NUMBER
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string
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default "H110M"
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config MAX_CPUS
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int
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default 8
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config DEVICETREE
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string
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default "devicetree.cb"
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0xd00
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config DIMM_SPD_SIZE
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int
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default 512 #DDR4
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# This is overridden if CMOS is used for configuration values.
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config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
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bool
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default n
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endif
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config BOARD_ASROCK_H110M_DVS
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bool "H110M-DVS"
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2013 Google Inc.
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## Copyright (C) 2016 Intel Corporation.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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subdirs-y += spd
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bootblock-y += bootblock.c
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ramstage-y += mainboard.c
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ramstage-y += ramstage.c
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ramstage-y += hda_verb.c
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ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define DPTF_CPU_PASSIVE 98
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#define DPTF_CPU_CRITICAL 125
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#define DPTF_CPU_ACTIVE_AC0 91
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#define DPTF_CPU_ACTIVE_AC1 85
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#define DPTF_CPU_ACTIVE_AC2 83
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#define DPTF_CPU_ACTIVE_AC3 80
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#define DPTF_CPU_ACTIVE_AC4 75
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Name (DTRT, Package () {
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/* CPU Throttle Effect on CPU */
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Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
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})
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Name (MPPC, Package ()
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{
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0x2, /* Revision */
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Package () { /* Power Limit 1 */
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0, /* PowerLimitIndex, 0 for Power Limit 1 */
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10000, /* PowerLimitMinimum */
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31000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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28000, /* TimeWindowMaximum */
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100 /* StepSize */
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},
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Package () { /* Power Limit 2 */
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1, /* PowerLimitIndex, 1 for Power Limit 2 */
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15000, /* PowerLimitMinimum */
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65000, /* PowerLimitMaximum */
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28000, /* TimeWindowMinimum */
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28000, /* TimeWindowMaximum */
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100 /* StepSize */
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}
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})
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/* Include DPTF */
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#include <soc/intel/skylake/acpi/dptf/dptf.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#define NCT6776_SHOW_PP
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#define NCT6776_SHOW_SP1
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#define NCT6776_SHOW_KBC
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#define NCT6776_SHOW_HWM
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#undef NCT6776_SHOW_GPIO
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#include <superio/nuvoton/nct6776/acpi/superio.asl>
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@ -0,0 +1,7 @@
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Category: desktop
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Board URL: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/
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ROM package: DIP-8
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ROM protocol: SPI
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ROM socketed: y
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Flashrom support: y
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Release year: 2015
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6791d/nct6791d.h>
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#include "include/gpio.h"
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static void early_config_superio(void)
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{
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const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1);
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nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
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}
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static void early_config_gpio(void)
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{
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/* This is a hack for FSP because it does things in MemoryInit()
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* which it shouldn't do. We have to prepare certain gpios here
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* because of the brokenness in FSP. */
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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}
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void bootblock_mainboard_early_init(void)
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{
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early_config_superio();
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}
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@ -0,0 +1,4 @@
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boot_option=Fallback
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debug_level=Debug
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power_on_after_fail=Disable
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nmi=Enable
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@ -0,0 +1,125 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2016 Intel Corporation.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
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|
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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# -----------------------------------------------------------------
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# Status Register A
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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# -----------------------------------------------------------------
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# Status Register B
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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||||
# -----------------------------------------------------------------
|
||||
0 120 r 0 reserved_memory
|
||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
388 4 h 0 reboot_counter
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
#392 3 r 0 unused
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
400 1 e 2 hyper_threading
|
||||
#401 7 r 0 unused
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
#411 5 r 0 unused
|
||||
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
#544 440 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
#1000 24 r 0 amd_reserved
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
6 0 Emergency
|
||||
6 1 Alert
|
||||
6 2 Critical
|
||||
6 3 Error
|
||||
6 4 Warning
|
||||
6 5 Notice
|
||||
6 6 Info
|
||||
6 7 Debug
|
||||
6 8 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
Binary file not shown.
|
|
@ -0,0 +1,367 @@
|
|||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2017 Intel Corporation.
|
||||
## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
chip soc/intel/skylake
|
||||
|
||||
# Enable deep Sx states
|
||||
register "deep_s3_enable_ac" = "0"
|
||||
register "deep_s3_enable_dc" = "0"
|
||||
register "deep_s5_enable_ac" = "0"
|
||||
register "deep_s5_enable_dc" = "0"
|
||||
register "deep_sx_config" = "DSX_EN_WAKE_PIN"
|
||||
|
||||
register "eist_enable" = "1"
|
||||
|
||||
# GPE configuration
|
||||
# Note that GPE events called out in ASL code rely on this
|
||||
# route. i.e. If this route changes then the affected GPE
|
||||
# offset bits also need to be changed.
|
||||
register "gpe0_dw0" = "GPP_B"
|
||||
register "gpe0_dw1" = "GPP_D"
|
||||
register "gpe0_dw2" = "GPP_E"
|
||||
|
||||
# Enable "Intel Speed Shift Technology"
|
||||
register "speed_shift_enable" = "1"
|
||||
|
||||
# Enable DPTF
|
||||
register "dptf_enable" = "1"
|
||||
|
||||
# FSP Configuration
|
||||
register "SmbusEnable" = "1"
|
||||
register "ScsEmmcEnabled" = "0"
|
||||
register "ScsEmmcHs400Enabled" = "0"
|
||||
register "ScsSdCardEnabled" = "0"
|
||||
register "HeciEnabled" = "0"
|
||||
register "InternalGfx" = "1"
|
||||
register "SkipExtGfxScan" = "0"
|
||||
register "Device4Enable" = "1"
|
||||
register "SaGv" = "SaGv_Enabled"
|
||||
register "PmTimerDisabled" = "0"
|
||||
register "EnableAzalia" = "1"
|
||||
register "DspEnable" = "0"
|
||||
|
||||
register "pirqa_routing" = "PCH_IRQ11"
|
||||
register "pirqb_routing" = "PCH_IRQ10"
|
||||
register "pirqc_routing" = "PCH_IRQ11"
|
||||
register "pirqd_routing" = "PCH_IRQ11"
|
||||
register "pirqe_routing" = "PCH_IRQ11"
|
||||
register "pirqf_routing" = "PCH_IRQ11"
|
||||
register "pirqg_routing" = "PCH_IRQ11"
|
||||
register "pirqh_routing" = "PCH_IRQ11"
|
||||
|
||||
# Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
|
||||
# SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
|
||||
register "PmConfigSlpS3MinAssert" = "0x02"
|
||||
|
||||
# SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
|
||||
register "PmConfigSlpS4MinAssert" = "0x04"
|
||||
|
||||
# SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
|
||||
register "PmConfigSlpSusMinAssert" = "0x03"
|
||||
|
||||
# SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
|
||||
register "PmConfigSlpAMinAssert" = "0x03"
|
||||
|
||||
# VR Settings Configuration for 5 Domains
|
||||
#+----------------+-------+-------+-------------+-------------+-------+
|
||||
#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
|
||||
#+----------------+-------+-------+-------------+-------------+-------+
|
||||
#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
|
||||
#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
|
||||
#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
|
||||
#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
|
||||
#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
|
||||
#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
|
||||
#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
|
||||
#| IccMax | 7A | 34A | 34A | 35A | 35A |
|
||||
#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
|
||||
#+----------------+-------+-------+-------------+-------------+-------+
|
||||
register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = 0x50, \
|
||||
.psi2threshold = 0x10, \
|
||||
.psi3threshold = 0x4, \
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 1, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0x0, \
|
||||
.voltage_limit = 0x0 \
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_IA_CORE]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = 0x50, \
|
||||
.psi2threshold = 0x14, \
|
||||
.psi3threshold = 0x4, \
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 1, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0x0, \
|
||||
.voltage_limit = 0x0 \
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_UNSLICED]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = 0x50, \
|
||||
.psi2threshold = 0x14, \
|
||||
.psi3threshold = 0x4, \
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 1, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0x0 ,\
|
||||
.voltage_limit = 0x0 \
|
||||
}"
|
||||
|
||||
register "domain_vr_config[VR_GT_SLICED]" = "{
|
||||
.vr_config_enable = 1, \
|
||||
.psi1threshold = 0x50, \
|
||||
.psi2threshold = 0x14, \
|
||||
.psi3threshold = 0x4, \
|
||||
.psi3enable = 1, \
|
||||
.psi4enable = 1, \
|
||||
.imon_slope = 0x0, \
|
||||
.imon_offset = 0x0, \
|
||||
.icc_max = 0x0, \
|
||||
.voltage_limit = 0x0 \
|
||||
}"
|
||||
|
||||
register "EnableLan" = "0"
|
||||
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
|
||||
|
||||
register "PmTimerDisabled" = "0"
|
||||
|
||||
# USB
|
||||
register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC4)"
|
||||
register "usb2_ports[3]" = "USB2_PORT_MID(OC4)"
|
||||
register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
|
||||
register "usb2_ports[10]" = "USB2_PORT_MID(OC1)"
|
||||
register "usb2_ports[11]" = "USB2_PORT_MID(OC1)"
|
||||
register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)"
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)"
|
||||
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)"
|
||||
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)"
|
||||
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)"
|
||||
|
||||
# SATA
|
||||
register "EnableSata" = "1"
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataPortsEnable" = "{ \
|
||||
[0] = 1, \
|
||||
[1] = 1, \
|
||||
[2] = 1, \
|
||||
[3] = 1, \
|
||||
[4] = 1, \
|
||||
[5] = 1, \
|
||||
[6] = 1, \
|
||||
[7] = 1, \
|
||||
}"
|
||||
|
||||
# PCH UART, SPI, I2C
|
||||
register "SerialIoDevMode" = "{ \
|
||||
[PchSerialIoIndexI2C0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C1] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexSpi0] = PchSerialIoPci, \
|
||||
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
|
||||
[PchSerialIoIndexUart2] = PchSerialIoDisabled, \
|
||||
}"
|
||||
|
||||
# Enable Root port 6(x1) for LAN.
|
||||
register "PcieRpEnable[5]" = "1"
|
||||
# Enable CLKREQ#
|
||||
register "PcieRpClkReqSupport[5]" = "1"
|
||||
# Use SRCCLKREQ1#
|
||||
register "PcieRpClkReqNumber[5]" = "1"
|
||||
# Enable Advanced Error Reporting
|
||||
register "PcieRpAdvancedErrorReporting[5]" = "1"
|
||||
# Enable Latency Tolerance Reporting Mechanism
|
||||
register "PcieRpLtrEnable[5]" = "1"
|
||||
# Use CLK SRC 1
|
||||
register "PcieRpClkSrcNumber[5]" = "1"
|
||||
|
||||
# Enable Root port 5 (x1) for PCIE slot.
|
||||
register "PcieRpEnable[4]" = "1"
|
||||
# Enable CLKREQ#
|
||||
register "PcieRpClkReqSupport[4]" = "1"
|
||||
# Use SRCCLKREQ2#
|
||||
register "PcieRpClkReqNumber[4]" = "2"
|
||||
# Enable Advanced Error Reporting
|
||||
register "PcieRpAdvancedErrorReporting[4]" = "1"
|
||||
# Enable Latency Tolerance Reporting Mechanism
|
||||
register "PcieRpLtrEnable[4]" = "1"
|
||||
# Use CLK SRC 2
|
||||
register "PcieRpClkSrcNumber[4]" = "2"
|
||||
# Use Hot Plug subsystem
|
||||
register "PcieRpHotPlug[4]" = "1"
|
||||
|
||||
# Enable Root port 7(x1) for PCIE slot.
|
||||
register "PcieRpEnable[6]" = "1"
|
||||
# Enable CLKREQ#
|
||||
register "PcieRpClkReqSupport[6]" = "1"
|
||||
# Use SRCCLKREQ3#
|
||||
register "PcieRpClkReqNumber[6]" = "3"
|
||||
# Enable Advanced Error Reporting
|
||||
register "PcieRpAdvancedErrorReporting[6]" = "1"
|
||||
# Enable Latency Tolerance Reporting Mechanism
|
||||
register "PcieRpLtrEnable[6]" = "1"
|
||||
# Use CLK SRC 3
|
||||
register "PcieRpClkSrcNumber[6]" = "3"
|
||||
# Use Hot Plug subsystem
|
||||
register "PcieRpHotPlug[6]" = "1"
|
||||
|
||||
# PL2 override 91W
|
||||
register "tdp_pl2_override" = "91"
|
||||
|
||||
# Send an extra VR mailbox command for the PS4 exit issue
|
||||
register "SendVrMbxCmd" = "2"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
device lapic 0 on end
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on # Host Bridge
|
||||
subsystemid 0x1849 0x191f
|
||||
end
|
||||
device pci 01.0 on # PEG
|
||||
subsystemid 0x1849 0x1901
|
||||
end
|
||||
device pci 02.0 on # Integrated Graphics Device
|
||||
subsystemid 0x1849 0x1912
|
||||
end
|
||||
device pci 14.0 on # USB xHCI
|
||||
subsystemid 0x1849 0xa131
|
||||
end
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
device pci 14.2 on # Thermal Subsystem
|
||||
subsystemid 0x1849 0xa131
|
||||
end
|
||||
device pci 15.0 off end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on # Management Engine Interface 1
|
||||
subsystemid 0x1849 0xa131
|
||||
end
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 17.0 on # SATA
|
||||
subsystemid 0x1849 0xa102
|
||||
end
|
||||
device pci 19.0 off end # UART #2
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 off end # I2C #4
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 on end # PCI Express Port 6
|
||||
device pci 1c.6 on end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 off end # PCI Express Port 9
|
||||
device pci 1d.1 off end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1e.4 off end # eMMC
|
||||
device pci 1e.5 off end # SDIO
|
||||
device pci 1e.6 off end # SDCard
|
||||
device pci 1f.0 on # LPC bridge
|
||||
subsystemid 0x1849 0x1a43
|
||||
chip superio/nuvoton/nct6791d
|
||||
device pnp 2e.0 off end # Floppy
|
||||
device pnp 2e.1 on # Parallel
|
||||
# global
|
||||
irq 0x1c = 0x10
|
||||
irq 0x27 = 0x10
|
||||
irq 0x2a = 0x64
|
||||
# parallel port
|
||||
io 0x60 = 0x0378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 4 # No DMA
|
||||
irq 0xf0 = 0x3c # Printer mode
|
||||
end
|
||||
device pnp 2e.2 on # UART A
|
||||
io 0x60 = 0x03f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # IR
|
||||
io 0x60 = 0x02f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 KBC
|
||||
io 0x60 = 0x0060
|
||||
io 0x62 = 0x0064
|
||||
irq 0x70 = 1 # Keyboard
|
||||
irq 0x72 = 12 # Mouse
|
||||
end
|
||||
device pnp 2e.6 off end # CIR
|
||||
device pnp 2e.7 off end # GPIO6..8
|
||||
# WDT1, WDT_MEM, GPIO 0, GPIO 1
|
||||
device pnp 2e.8 off end
|
||||
# GPIO 2, GPIO 3, GPIO 4, GPIO 5
|
||||
device pnp 2e.9 off end
|
||||
device pnp 2e.a off end # ACPI
|
||||
device pnp 2e.b on # HWM, LED
|
||||
io 0x60 = 0x0290
|
||||
io 0x62 = 0
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.d off end # BCLK, WDT2, WDT_MEM
|
||||
device pnp 2e.e off end # CIR wake-up
|
||||
device pnp 2e.f off end # GPIO PP/OD
|
||||
device pnp 2e.14 off end # SVID, Port 80 UART
|
||||
device pnp 2e.16 off end # Deep sleep
|
||||
end # superio/nuvoton/nct6791d
|
||||
chip drivers/pc80/tpm
|
||||
device pnp 4e.0 on end # TPM module
|
||||
end
|
||||
end # LPC Interface
|
||||
device pci 1f.1 on end # P2SB
|
||||
device pci 1f.2 on end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2015 Google Inc.
|
||||
* Copyright (C) 2016 Intel Corporation
|
||||
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/acpi.h>
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0 and up
|
||||
OEM_ID,
|
||||
ACPI_TABLE_CREATOR,
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
#include <soc/intel/skylake/acpi/platform.asl>
|
||||
|
||||
// global NVS and variables
|
||||
#include <soc/intel/skylake/acpi/globalnvs.asl>
|
||||
|
||||
// CPU
|
||||
#include <cpu/intel/common/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
/* Image processing unit */
|
||||
#include <soc/intel/skylake/acpi/ipu.asl>
|
||||
#include <soc/intel/skylake/acpi/systemagent.asl>
|
||||
#include <soc/intel/skylake/acpi/pch.asl>
|
||||
}
|
||||
|
||||
// Dynamic Platform Thermal Framework
|
||||
#include "acpi/dptf.asl"
|
||||
}
|
||||
|
||||
// Chipset specific sleep states
|
||||
#include <soc/intel/skylake/acpi/sleepstates.asl>
|
||||
|
||||
// Mainboard specific
|
||||
#include "acpi/mainboard.asl"
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
--
|
||||
-- This file is part of the coreboot project.
|
||||
--
|
||||
-- Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
--
|
||||
-- This program is free software: you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation, either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
|
||||
with HW.GFX.GMA;
|
||||
with HW.GFX.GMA.Display_Probing;
|
||||
|
||||
use HW.GFX.GMA;
|
||||
use HW.GFX.GMA.Display_Probing;
|
||||
|
||||
private package GMA.Mainboard is
|
||||
|
||||
ports : constant Port_List :=
|
||||
(HDMI1, -- mainboard DVI port
|
||||
HDMI3, -- mainboard HDMI port
|
||||
Analog,
|
||||
others => Disabled);
|
||||
|
||||
end GMA.Mainboard;
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2017 Intel Corporation
|
||||
* (Written by Naresh G Solanki <naresh.solanki@intel.com> for Intel Corp.)
|
||||
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header ALC887 */
|
||||
0x10ec0887, /* Codec Vendor / Device ID: Realtek */
|
||||
0x10438445, /* Subsystem ID */
|
||||
15, /* Number of 4 dword sets */
|
||||
AZALIA_SUBVENDOR(0x0, 0x10438445),
|
||||
AZALIA_PIN_CFG(0x0, 0x11, 0x40000000),
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x01014020),
|
||||
AZALIA_PIN_CFG(0x0, 0x15, 0x90170110),
|
||||
AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040),
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050),
|
||||
AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f),
|
||||
AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030),
|
||||
AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629),
|
||||
AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),
|
||||
|
||||
/* coreboot specific header */
|
||||
0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */
|
||||
0x80860101,
|
||||
0x00000004,
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
|
||||
AZALIA_SUBVENDOR(0x2, 0x80860101),
|
||||
|
||||
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
|
||||
AZALIA_PIN_CFG(0x2, 0x05, 0x18560010),
|
||||
|
||||
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
|
||||
AZALIA_PIN_CFG(0x2, 0x06, 0x18560020),
|
||||
|
||||
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
|
||||
AZALIA_PIN_CFG(0x2, 0x07, 0x18560030)
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
};
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _GPIO_DVS_H
|
||||
#define _GPIO_DVS_H
|
||||
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \
|
||||
_PAD_CFG_STRUCT(val, config0, config1)
|
||||
|
||||
/* Pad configuration in ramstage. */
|
||||
static const struct pad_config gpio_table[] = {
|
||||
/* GPIO Group GPP_A */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */
|
||||
/* GPIO Group GPP_B */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */
|
||||
/* GPIO Group GPP_C */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */
|
||||
/* GPP_C6 - RESERVED */
|
||||
/* GPP_C7 - RESERVED */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */
|
||||
/* GPIO Group GPP_D */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */
|
||||
/* GPIO Group GPP_E */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */
|
||||
/* SATA_DEVSLP0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c),
|
||||
/* SATA_DEVSLP1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d),
|
||||
/* SATA_DEVSLP2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e),
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */
|
||||
/* GPIO Group GPP_F */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */
|
||||
/* GPIO Group GPP_G */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */
|
||||
/* GPIO Group GPP_H */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */
|
||||
/* GPIO Group GPD */
|
||||
H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */
|
||||
H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */
|
||||
H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */
|
||||
/* GPIO Group GPP_I */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */
|
||||
/* DDPB_CTRLCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072),
|
||||
/* DDPB_CTRLDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073),
|
||||
/* DDPC_CTRLCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074),
|
||||
/* DDPC_CTRLDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075),
|
||||
/* DDPD_CTRLCLK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076),
|
||||
/* DDPD_CTRLDATA */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077),
|
||||
};
|
||||
|
||||
/* Early pad configuration in romstage. */
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
/* GPIO Group GPP_A */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */
|
||||
/* ---- */
|
||||
/* SUSWARN#/SUSPWRDNACK */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025),
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */
|
||||
H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2018 Tristan Corrick <tristan@corrick.kiwi>
|
||||
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
*
|
||||
* This program is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Intel Corporation
|
||||
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/ramstage.h>
|
||||
#include "include/gpio.h"
|
||||
|
||||
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
|
||||
{
|
||||
/* Configure pads prior to SiliconInit() in case there's any
|
||||
* dependencies during hardware initialization. */
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
|
||||
params->CdClock = 3;
|
||||
/* Enable Virtual Channel 1 */
|
||||
params->PchHdaVcType = 0x1;
|
||||
}
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2016 Intel Corporation.
|
||||
* Copyright (C) 2019 Maxim Polyakov <max.senia.poliak@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <soc/romstage.h>
|
||||
#include <string.h>
|
||||
#include <spd_bin.h>
|
||||
|
||||
#define RCOMP_TARGET_PARAMS 0x5
|
||||
|
||||
static void mainboard_fill_dq_map_data(void *dq_map_ptr)
|
||||
{
|
||||
/* DQ byte map */
|
||||
const u8 dq_map[2][12] = {
|
||||
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
|
||||
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||
memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
|
||||
}
|
||||
|
||||
static void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
|
||||
{
|
||||
/* DQS CPU<>DRAM map */
|
||||
const u8 dqs_map[2][8] = {
|
||||
{ 0, 1, 3, 2, 4, 5, 6, 7 },
|
||||
{ 1, 0, 4, 5, 2, 3, 6, 7 } };
|
||||
memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
|
||||
}
|
||||
|
||||
static void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
|
||||
{
|
||||
/* Rcomp resistor */
|
||||
const u16 RcompResistor[3] = { 200, 81, 162 };
|
||||
memcpy(rcomp_ptr, RcompResistor,
|
||||
sizeof(RcompResistor));
|
||||
}
|
||||
|
||||
static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
|
||||
{
|
||||
/* Rcomp target */
|
||||
static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
|
||||
100, 40, 40, 23, 40 };
|
||||
memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
FSP_M_CONFIG *mem_cfg;
|
||||
struct spd_block blk = {
|
||||
.addr_map = { 0x50, 0x51, 0x52, 0x53, },
|
||||
};
|
||||
|
||||
mem_cfg = &mupd->FspmConfig;
|
||||
mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
|
||||
mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
|
||||
mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
|
||||
mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
|
||||
|
||||
mem_cfg->DqPinsInterleaved = 1;
|
||||
get_spd_smbus(&blk);
|
||||
mem_cfg->MemorySpdDataLen = blk.len;
|
||||
mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
|
||||
mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2];
|
||||
mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1];
|
||||
mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
|
||||
dump_spd_info(&blk);
|
||||
|
||||
/* use virtual channel 1 for the dmi interface of the PCH */
|
||||
mupd->FspmTestConfig.DmiVc1 = 1;
|
||||
|
||||
/* desktop type */
|
||||
mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
|
||||
}
|
||||
Loading…
Reference in New Issue