From 122e1dfe5d992788b636e803dd9aa76ba5497220 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 9 Dec 2022 12:32:12 +0100 Subject: [PATCH] soc/intel/alderlake/Kconfig: Sort defaults alphabetically MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "Argh! Lack of consistency! UNACCEPTABLE!" - Emotions Swap the position of two lines so that defaults are listed in alphabetical order according to the PCH type: M, N, P, S. Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522 Reviewed-by: Subrata Banik Reviewed-by: Michał Żygowski Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/soc/intel/alderlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5b624d8ae1..5f24e37036 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -252,8 +252,8 @@ config MAX_PCIE_CLOCK_SRC int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N - default 18 if SOC_INTEL_ALDERLAKE_PCH_S default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S help With external clock buffer, Alderlake-P can support up to three additional source clocks. This is done by setting the corresponding GPIO pin(s) to native function to use as