mb/intel/mtlrvp: Add romstage and configure DDR5 memory parts

This patch adds initial romstage code and spd data for DDR5 memory
parts for MTL-RVP. This also configures memory based on the board id.

Memory - x32 DDR5 SBS SODIMM 1DPC
Vendor/Model - SK-Hynix/HMCG66MEBSA092N

BUG=b:224325352
TEST=Able to boot intel/mtlrvp (DDR5 SKU) to ChromeOS

Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I0e1a26d99e170311a89412f44b7cbb0430788f58
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/mainboard/intel/mtlrvp/Makefile.inc

@@ -4,6 +4,8 @@ all-$(CONFIG_CHROMEOS) += chromeos.c
 
 bootblock-y += bootblock.c
 
+romstage-y += romstage.c
+
 ramstage-y += ec.c
 ramstage-y += mainboard.c
 
@@ -13,6 +15,7 @@ VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
 BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
 
 subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
+subdirs-y += variants/baseboard/$(BASEBOARD_DIR)/memory
 subdirs-y += variants/$(VARIANT_DIR)
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

src/mainboard/intel/mtlrvp/romstage.c

@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <ec/intel/board_id.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+	const struct mb_cfg *mem_config = variant_memory_params();
+	int board_id = get_rvp_board_id();
+	const bool half_populated = false;
+
+	const struct mem_spd dimm_module_spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = {
+				.addr_dimm[0] = 0x50,
+				.addr_dimm[1] = 0x0,
+			},
+			[1] = {
+				.addr_dimm[0] = 0x50,
+				.addr_dimm[1] = 0x0,
+			},
+			[2] = {
+				.addr_dimm[0] = 0x52,
+				.addr_dimm[1] = 0x0,
+			},
+			[3] = {
+				.addr_dimm[0] = 0x52,
+				.addr_dimm[1] = 0x0,
+			},
+		},
+	};
+
+	switch (board_id) {
+	case MTLP_DDR5_RVP:
+		memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
+		break;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
+}

src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h

@@ -3,6 +3,7 @@
 #ifndef __BASEBOARD_VARIANTS_H__
 #define __BASEBOARD_VARIANTS_H__
 
+#include <soc/meminit.h>
 #include <stdint.h>
 
 enum mtl_boardid {
@@ -16,4 +17,7 @@ enum mtl_boardid {
 void configure_early_gpio_pads(void);
 void configure_gpio_pads(void);
 
+/* Function to initialize memory params based on variant */
+const struct mb_cfg *variant_memory_params(void);
+
 #endif /*__BASEBOARD_VARIANTS_H__ */

src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/Makefile.inc

@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+romstage-y += memory.c

src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/memory/memory.c

@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <ec/intel/board_id.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr5_mem_config = {
+	.type = MEM_TYPE_DDR5,
+
+	.rcomp = {
+		/* As per doc #729782, baseboard uses only 100 Ohm Rcomp resistor */
+		.resistor = 100,
+	},
+
+	.ect = true, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_ULT_ULX,
+
+	.LpDdrDqDqsReTraining = 1,
+
+	.ddr_config = {
+		.dq_pins_interleaved = false,
+	}
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+	int board_id = get_rvp_board_id();
+
+	switch (board_id) {
+	case MTLP_DDR5_RVP:
+		return &ddr5_mem_config;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
+}