samus: Disable CMDPWR on broadwell
Workaround for auto shutdown issue on broadwell SKU. Now we can see C7 transition, and MRC fastboot BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build ok and boot on samus Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e Original-Reviewed-on: https://chromium-review.googlesource.com/210870 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: Kane Chen <kane.chen@intel.com> Original-Commit-Queue: Kane Chen <kane.chen@intel.com> (cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a Reviewed-on: http://review.coreboot.org/8950 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@ -59,8 +59,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
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* Disable use of PEI saved data to work around memory issues.
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* Disable use of PEI saved data to work around memory issues.
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*/
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*/
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if (cpu_family_model() == BROADWELL_FAMILY_ULT) {
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if (cpu_family_model() == BROADWELL_FAMILY_ULT) {
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pei_data.disable_self_refresh = 1;
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pei_data.disable_cmd_pwr = 1;
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pei_data.disable_saved_data = 1;
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}
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}
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/* Initalize memory */
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/* Initalize memory */
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@ -124,6 +124,8 @@ struct pei_data
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int max_ddr3_freq;
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int max_ddr3_freq;
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/* Disable self refresh */
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/* Disable self refresh */
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int disable_self_refresh;
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int disable_self_refresh;
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/* Disable cmd power/CKEPD */
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int disable_cmd_pwr;
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/* USB port configuration */
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/* USB port configuration */
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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