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samus: Disable CMDPWR on broadwell 

Workaround for auto shutdown issue on broadwell SKU.
Now we can see C7 transition, and MRC fastboot

BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build ok and boot on samus

Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Id: 932152b16c3943b00bd317e7370402dda451529f
Original-Change-Id: Id1f174b67fa3e6f248dd8b21aee25e6e01abf33e
Original-Reviewed-on: https://chromium-review.googlesource.com/210870
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
(cherry picked from commit 932152b16c3943b00bd317e7370402dda451529f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Ie9fb792635b39d33136cef576ae5559013d5947a
Reviewed-on: http://review.coreboot.org/8950
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Kane Chen 2014-08-01 10:59:20 -07:00 committed by Marc Jones
parent 84b9cf4756
commit 124f53fa99
2 changed files with 3 additions and 2 deletions
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3
src/mainboard/google/samus/romstage.c
View File

@ -59,8 +59,7 @@ void mainboard_romstage_entry(struct romstage_params *rp)
* Disable use of PEI saved data to work around memory issues.
*/
if (cpu_family_model() == BROADWELL_FAMILY_ULT) {
pei_data.disable_self_refresh = 1;
pei_data.disable_saved_data = 1;
pei_data.disable_cmd_pwr = 1;
}
/* Initalize memory */

2
src/soc/intel/broadwell/broadwell/pei_data.h
View File

@ -124,6 +124,8 @@ struct pei_data
int max_ddr3_freq;
/* Disable self refresh */
int disable_self_refresh;
/* Disable cmd power/CKEPD */
int disable_cmd_pwr;
/* USB port configuration */
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];