mb/google/geralt: Enable Chrome EC
Initialize SPI bus 0 for Chrome EC control. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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@ -8,17 +8,22 @@ if BOARD_GOOGLE_GERALT_COMMON
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config VBOOT
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select VBOOT_VBNV_FLASH
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select EC_GOOGLE_CHROMEEC_SWITCHES
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select SOC_MEDIATEK_MT8188
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select BOARD_ROMSIZE_KB_8192
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select MAINBOARD_HAS_CHROMEOS
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select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
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select COMMON_CBFS_SPI_WRAPPER
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select SPI_FLASH
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select SPI_FLASH_INCLUDE_ALL_DRIVERS
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select COMMONLIB_STORAGE
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select COMMONLIB_STORAGE_MMC
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_SPI
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config MAINBOARD_DIR
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string
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@ -31,4 +36,8 @@ config MAINBOARD_PART_NUMBER
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config BOOT_DEVICE_SPI_FLASH_BUS
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int
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default 7
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config EC_GOOGLE_CHROMEEC_SPI_BUS
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hex
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default 0x0
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endif
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@ -6,5 +6,6 @@
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void bootblock_mainboard_init(void)
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{
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mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
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mtk_snfc_init();
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}
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@ -7,9 +7,3 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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{
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/* TODO: add Chrome specific gpios */
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}
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int get_recovery_mode_switch(void)
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{
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/* TODO: use Chrome EC switches when EC support is added */
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return 0;
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}
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@ -0,0 +1,12 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __MAINBOARD_GOOGLE_GERALT_GPIO_H__
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#define __MAINBOARD_GOOGLE_GERALT_GPIO_H__
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#include <soc/gpio.h>
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#define GPIO_AP_EC_WARM_RST_REQ GPIO(DPI_HSYNC)
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void setup_chromeos_gpios(void);
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#endif
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@ -1,8 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <gpio.h>
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#include <reset.h>
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#include "gpio.h"
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void do_board_reset(void)
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{
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/* TODO: add reset function when gpio is ready */
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gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1);
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}
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