Drop console/console.c and pc80/serial.c from mainboards'

romstage.c.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/console/Makefile.inc

@@ -7,6 +7,7 @@ smmobj-y += printk.o
 smmobj-y += vtxprintf.o
 
 initobj-y += vtxprintf.o
+initobj-$(CONFIG_USE_DCACHE_RAM) += console.o
 
 driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.o
 driver-$(CONFIG_USBDEBUG_DIRECT) += usbdebug_direct_console.o

src/console/console.c

@@ -5,9 +5,9 @@
 #include <console/console.h>
 #include <build.h>
 #include <arch/hlt.h>
+#include <arch/io.h>
 
 #ifndef __PRE_RAM__
-#include <arch/io.h>
 #include <string.h>
 #include <pc80/mc146818rtc.h>
 

src/include/console/console.h

@@ -307,4 +307,9 @@ static void print_spew(const char *str) { __console_tx_string(BIOS_SPEW, str); }
 
 #endif
 
+#ifdef __ROMCC__
+/* if included by romcc, include the sources, too. romcc can't use prototypes */
+#include <console/console.c>
+#endif
+
 #endif /* CONSOLE_CONSOLE_H_ */

src/mainboard/a-trend/atc-6220/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/a-trend/atc-6240/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/abit/be6-ii_v2_0/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/advantech/pcm-5820/romstage.c

@@ -24,7 +24,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"

src/mainboard/amd/db800/romstage.c

@@ -19,13 +19,12 @@
  */
 
 #include <stdint.h>
+#include <stdlib.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
 #include <console/console.h>
-#include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"
@@ -33,7 +32,6 @@
 #include <cpu/amd/geode_post_code.h>
 #include "southbridge/amd/cs5536/cs5536.h"
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
 #include "southbridge/amd/cs5536/cs5536_early_smbus.c"

src/mainboard/amd/dbm690t/romstage.c

@@ -42,8 +42,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/amd/mahogany/romstage.c

@@ -42,8 +42,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -47,8 +47,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"

src/mainboard/amd/norwich/romstage.c

@@ -23,8 +23,7 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/amd/pistachio/romstage.c

@@ -36,8 +36,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/amd/rumba/romstage.c

@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"

src/mainboard/amd/serengeti_cheetah/romstage.c

@@ -29,8 +29,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include <reset.h>

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -47,8 +47,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -47,8 +47,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "console/console.c"
-#include "pc80/serial.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include <cpu/amd/model_10xxx_rev.h>
 #include "northbridge/amd/amdfam10/raminit.h"

src/mainboard/arima/hdama/romstage.c

@@ -7,8 +7,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/artecgroup/dbe61/romstage.c

@@ -25,8 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include <stdlib.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/asi/mb_5blgp/romstage.c

@@ -24,7 +24,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "cpu/x86/bist.h"

src/mainboard/asi/mb_5blmp/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc87351/pc87351_early_serial.c"

src/mainboard/asrock/939a785gmh/romstage.c

@@ -43,8 +43,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/asus/a8n_e/romstage.c

@@ -48,8 +48,7 @@
 #define CK804_NUM 1
 
 #include <cpu/amd/model_fxx_rev.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"

src/mainboard/asus/a8v-e_se/romstage.c

@@ -46,8 +46,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

src/mainboard/asus/m2v-mx_se/romstage.c

@@ -51,8 +51,7 @@ unsigned int get_sbdn(unsigned bus);
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"

src/mainboard/asus/mew-am/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/asus/mew-vm/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/asus/p2b-d/romstage.c

@@ -27,7 +27,7 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/asus/p2b-ds/romstage.c

@@ -27,7 +27,7 @@
 #include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/asus/p2b-f/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/asus/p2b-ls/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/asus/p2b/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/asus/p3b-f/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/axus/tc320/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"

src/mainboard/azza/pt-6ibd/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/bcom/winnet100/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/gx1/raminit.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"

src/mainboard/bcom/winnetp680/romstage.c

@@ -26,8 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/biostar/m6tba/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/broadcom/blast/romstage.c

@@ -13,8 +13,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/compaq/deskpro_en_sff_p600/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/dell/s1850/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"

src/mainboard/digitallogic/adl855pc/romstage.c

@@ -8,8 +8,7 @@
 #include <stdlib.h>
 #include "pc80/udelay_io.c"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801dx/i82801dx.h"
 #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"

src/mainboard/digitallogic/msm586seg/romstage.c

@@ -6,7 +6,7 @@
 #include <arch/hlt.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 //#include "lib/delay.c"

src/mainboard/digitallogic/msm800sev/romstage.c

@@ -4,8 +4,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/eaglelion/5bcm/romstage.c

@@ -6,7 +6,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 //#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
 #include "superio/nsc/pc97317/pc97317_early_serial.c"

src/mainboard/emulation/qemu-x86/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "cpu/x86/lapic/boot_cpu.c"

src/mainboard/gigabyte/ga-6bxc/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/gigabyte/ga_2761gxdk/romstage.c

@@ -53,8 +53,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/sis/sis966/sis966_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"

src/mainboard/gigabyte/m57sli/romstage.c

@@ -51,8 +51,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"

src/mainboard/hp/dl145_g3/romstage.c

@@ -57,8 +57,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/hp/e_vectra_p2706t/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 /* TODO: It's a PC87364 actually! */
 #include "superio/nsc/pc87360/pc87360_early_serial.c"

src/mainboard/ibm/e325/romstage.c

@@ -9,8 +9,7 @@
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/ibm/e326/romstage.c

@@ -9,8 +9,7 @@
 #include <stdlib.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/iei/juki-511p/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977f/w83977f_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"

src/mainboard/iei/nova4899r/romstage.c

@@ -25,7 +25,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83977tf/w83977tf_early_serial.c"
 #include "southbridge/amd/cs5530/cs5530_enable_rom.c"

src/mainboard/iei/pcisa-lx-800-r10/romstage.c

@@ -23,8 +23,7 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/intel/d945gclf/romstage.c

@@ -37,8 +37,6 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT

src/mainboard/intel/eagleheights/romstage.c

@@ -32,8 +32,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/x86/bist.h>
 
 #include "lib/ramtest.c"

src/mainboard/intel/jarrell/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"

src/mainboard/intel/mtarvon/romstage.c

@@ -28,7 +28,7 @@
 #include <cpu/x86/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"

src/mainboard/intel/truxton/romstage.c

@@ -29,7 +29,7 @@
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i3100/i3100_early_smbus.c"
 #include "southbridge/intel/i3100/i3100_early_lpc.c"

src/mainboard/intel/xe7501devkit/romstage.c

@@ -9,7 +9,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"

src/mainboard/iwill/dk8_htx/romstage.c

@@ -29,8 +29,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/iwill/dk8s2/romstage.c

@@ -29,8 +29,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/iwill/dk8x/romstage.c

@@ -29,8 +29,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/amd/amd8111/amd8111_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/jetway/j7f24/romstage.c

@@ -26,8 +26,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/via/cn700/raminit.h"
 #include "cpu/x86/mtrr/earlymtrr.c"

src/mainboard/kontron/986lcd-m/romstage.c

@@ -46,8 +46,6 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT

src/mainboard/kontron/kt690/romstage.c

@@ -43,8 +43,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "northbridge/amd/amdk8/raminit.h"

src/mainboard/lippert/frontrunner/romstage.c

@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"

src/mainboard/lippert/roadrunner-lx/romstage.c

@@ -27,8 +27,7 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/lippert/spacerunner-lx/romstage.c

@@ -28,8 +28,7 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/mitac/6513wu/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/msi/ms6119/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/msi/ms6147/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/msi/ms6156/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/msi/ms6178/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/msi/ms7135/romstage.c

@@ -50,8 +50,7 @@
 #define CK804_USE_ACI 1
 
 #include <cpu/amd/model_fxx_rev.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"

src/mainboard/msi/ms7260/romstage.c

@@ -55,8 +55,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"

src/mainboard/msi/ms9185/romstage.c

@@ -49,8 +49,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"

src/mainboard/msi/ms9282/romstage.c

@@ -44,8 +44,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 
 #include <cpu/amd/model_fxx_rev.h>
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"

src/mainboard/msi/ms9652_fam10/romstage.c

@@ -45,8 +45,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"

src/mainboard/nec/powermate2000/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82810/raminit.h"

src/mainboard/newisys/khepri/romstage.c

@@ -14,8 +14,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/nokia/ip530/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/nvidia/l1_2pvv/romstage.c

@@ -51,8 +51,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #if CONFIG_USBDEBUG_DIRECT
 #include "southbridge/nvidia/mcp55/mcp55_enable_usbdebug_direct.c"
 #include "pc80/usbdebug_direct_serial.c"

src/mainboard/olpc/btest/romstage.c

@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"

src/mainboard/olpc/rev_a/romstage.c

@@ -5,7 +5,7 @@
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "cpu/x86/bist.h"

src/mainboard/pcengines/alix1c/romstage.c

@@ -24,8 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"
 #include "cpu/x86/msr.h"

src/mainboard/rca/rm4100/romstage.c

@@ -25,9 +25,8 @@
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
 #include <arch/hlt.h>
-#include "pc80/serial.c"
 #include "pc80/udelay_io.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
 #include "northbridge/intel/i82830/raminit.h"

src/mainboard/roda/rk886ex/romstage.c

@@ -39,8 +39,6 @@
 #include "pc80/mc146818rtc_early.c"
 
 #include <console/console.h>
-#include "pc80/serial.c"
-#include "console/console.c"
 #include <cpu/x86/bist.h>
 
 #if CONFIG_USBDEBUG_DIRECT

src/mainboard/soyo/sy-6ba-plus-iii/romstage.c

@@ -26,7 +26,7 @@
 #include <arch/hlt.h>
 #include <stdlib.h>
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"

src/mainboard/sunw/ultra40/romstage.c

@@ -16,8 +16,7 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/supermicro/h8dme/romstage.c

@@ -46,8 +46,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/supermicro/h8dmr/romstage.c

@@ -49,8 +49,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_fxx_rev.h>

src/mainboard/supermicro/h8dmr_fam10/romstage.c

@@ -44,8 +44,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/supermicro/h8qme_fam10/romstage.c

@@ -44,8 +44,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 
-#include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 
 #include <cpu/amd/model_10xxx_rev.h>

src/mainboard/supermicro/x6dai_g/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"

src/mainboard/supermicro/x6dhe_g/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"

src/mainboard/supermicro/x6dhe_g2/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"

src/mainboard/supermicro/x6dhr_ig/romstage.c

@@ -8,7 +8,7 @@
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
-#include "console/console.c"
+#include <console/console.h>
 #include "lib/ramtest.c"
 #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
 #include "northbridge/intel/e7520/raminit.h"