diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 5f53c692c9..e6e44e2f56 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -1,10 +1,12 @@
 config BOARD_GOOGLE_BASEBOARD_BRYA
 	def_bool n
-	select ROMSTAGE_SPD_CBFS
+	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
+	select HAVE_SPD_IN_CBFS
 	select SYSTEM_TYPE_LAPTOP
 
 config BOARD_GOOGLE_BASEBOARD_BRASK
 	def_bool n
+	select SPD_CACHE_IN_FMAP
 
 if BOARD_GOOGLE_BASEBOARD_BRYA || BOARD_GOOGLE_BASEBOARD_BRASK
 
@@ -50,7 +52,6 @@ config BASEBOARD_DIR
 	default "brask" if BOARD_GOOGLE_BASEBOARD_BRASK
 
 config CHROMEOS
-	select CHROMEOS_DRAM_PART_NUMBER_IN_CBI
 	select EC_GOOGLE_CHROMEEC_SWITCHES
 	select HAS_RECOVERY_MRC_CACHE
 	select VBOOT_LID_SWITCH
@@ -118,10 +119,6 @@ config UART_FOR_CONSOLE
 	int
 	default 0
 
-config ROMSTAGE_SPD_CBFS
-	def_bool n
-	select HAVE_SPD_IN_CBFS
-
 config HAVE_WWAN_POWER_SEQUENCE
 	def_bool n
 	help
diff --git a/src/mainboard/google/brya/Makefile.inc b/src/mainboard/google/brya/Makefile.inc
index 5dabd84bab..c40f21c275 100644
--- a/src/mainboard/google/brya/Makefile.inc
+++ b/src/mainboard/google/brya/Makefile.inc
@@ -3,7 +3,7 @@ bootblock-y += bootblock.c
 verstage-$(CONFIG_CHROMEOS) += chromeos.c
 
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-$(CONFIG_ROMSTAGE_SPD_CBFS) += romstage_spd_cbfs.c
+romstage-y += romstage.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
 ramstage-y += mainboard.c
@@ -15,7 +15,7 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
 subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
 subdirs-y += variants/$(VARIANT_DIR)
 subdirs-y += variants/$(VARIANT_DIR)/memory
-subdirs-$(CONFIG_ROMSTAGE_SPD_CBFS) += spd
+subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include
diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd
index c1a4147af0..9e4bfa92c3 100644
--- a/src/mainboard/google/brya/chromeos.fmd
+++ b/src/mainboard/google/brya/chromeos.fmd
@@ -21,6 +21,11 @@ FLASH 32M {
 				SHARED_DATA 8K
 				VBLOCK_DEV 8K
 			}
+			# The RW_SPD_CACHE region is only used for brya variants that use DDRx memory.
+			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
+			# is free space in the RW_MISC region that cannot be easily reclaimed because
+			# the RW_SECTION_B must start on the 16M boundary.
+			RW_SPD_CACHE(PRESERVE) 4K
 			RW_VPD(PRESERVE) 8K
 			RW_NVRAM(PRESERVE) 24K
 		}
diff --git a/src/mainboard/google/brya/romstage_spd_cbfs.c b/src/mainboard/google/brya/romstage.c
similarity index 81%
rename from src/mainboard/google/brya/romstage_spd_cbfs.c
rename to src/mainboard/google/brya/romstage.c
index eadc2770d6..d50d6e8571 100644
--- a/src/mainboard/google/brya/romstage_spd_cbfs.c
+++ b/src/mainboard/google/brya/romstage.c
@@ -5,15 +5,17 @@
 #include <fsp/api.h>
 #include <gpio.h>
 #include <soc/romstage.h>
+#include <string.h>
 
 void mainboard_memory_init_params(FSP_M_CONFIG *m_cfg)
 {
 	const struct mb_cfg *mem_config = variant_memory_params();
 	bool half_populated = variant_is_half_populated();
-	const struct mem_spd spd_info = {
-		.topo = MEM_TOPO_MEMORY_DOWN,
-		.cbfs_index = variant_memory_sku(),
-	};
+	struct mem_spd spd_info;
+
+	memset(&spd_info, 0, sizeof(spd_info));
+	variant_get_spd_info(&spd_info);
+
 	const struct pad_config *pads;
 	size_t pads_num;
 
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
index 6c29346470..1693d2e263 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
+++ b/src/mainboard/google/brya/variants/baseboard/brask/Makefile.inc
@@ -1,5 +1,6 @@
 bootblock-y += gpio.c
 
+romstage-y += memory.c
 romstage-y += gpio.c
 
 ramstage-y += gpio.c
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
index 3b9acea22b..646309ecd7 100644
--- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb
@@ -149,5 +149,6 @@ chip soc/intel/alderlake
 			end
 		end
 		device ref hda on end
+		device ref smbus on end
 	end
 end
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/memory.c b/src/mainboard/google/brya/variants/baseboard/brask/memory.c
new file mode 100644
index 0000000000..2e24110bb1
--- /dev/null
+++ b/src/mainboard/google/brya/variants/baseboard/brask/memory.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg ddr4_mem_config = {
+	.type = MEM_TYPE_DDR4,
+
+	.rcomp = {
+		/* Baseboard uses only 100ohm Rcomp resistors */
+		.resistor = 100,
+
+		/* Baseboard Rcomp target values */
+		.targets = {50, 20, 25, 25, 25},
+	},
+
+	.ect = 1, /* Early Command Training */
+
+	.UserBd = BOARD_TYPE_MOBILE,
+
+	.ddr_config = {
+		.dq_pins_interleaved = 1,
+	},
+};
+
+const struct mb_cfg *__weak variant_memory_params(void)
+{
+	return &ddr4_mem_config;
+}
+
+bool __weak variant_is_half_populated(void)
+{
+	return false;
+}
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_DIMM_MODULE;
+	spd_info->smbus[0].addr_dimm[0] = 0x50;
+	spd_info->smbus[1].addr_dimm[0] = 0x52;
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/brya/memory.c b/src/mainboard/google/brya/variants/baseboard/brya/memory.c
index 2a0b6aca36..f04c97e608 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/memory.c
+++ b/src/mainboard/google/brya/variants/baseboard/brya/memory.c
@@ -95,3 +95,9 @@ bool __weak variant_is_half_populated(void)
 	/* GPIO_MEM_CH_SEL GPP_E13 */
 	return gpio_get(GPP_E13);
 }
+
+void __weak variant_get_spd_info(struct mem_spd *spd_info)
+{
+	spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+	spd_info->cbfs_index = variant_memory_sku();
+}
diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
index a2c1b4238c..3e0fd05105 100644
--- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
@@ -19,6 +19,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num);
 const struct pad_config *variant_romstage_gpio_table(size_t *num);
 
 const struct mb_cfg *variant_memory_params(void);
+void variant_get_spd_info(struct mem_spd *spd_info);
 int variant_memory_sku(void);
 bool variant_is_half_populated(void);
 void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config);