gigabyte/ga-b75m-d3h: Add new Intel mainboard
This is based on LENOVO X230 port. Board boots to linux via SATA or USB. All USB ports are working. Remaining Issues: 1. Native raminit sometimes fails with "timC write discovery failed" even without changing the ram configuration. I suggest altering the native raminit code so that it reboots if that message appears to give a chance for the boot process to recover. 2. VGA does not work. Native graphics initialization only supports LVDS and the VGA Option ROM still hangs when run in SeaBIOS. Change-Id: I91a7aab96d6c5f213b097cd55fcc47d4c94b3172 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/7341 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Damien Zammit
Edward O'Callaghan
parent
6d0cba7978
commit
126a2a8a78
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@ -27,6 +27,8 @@ config BOARD_GIGABYTE_GA_6BXC
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bool "GA-6BXC"
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config BOARD_GIGABYTE_GA_6BXE
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bool "GA-6BXE"
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config BOARD_GIGABYTE_GA_B75M_D3H
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bool "GA-B75M-D3H"
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config BOARD_GIGABYTE_M57SLI
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bool "GA-M57SLI-S4"
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config BOARD_GIGABYTE_MA785GMT
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@ -41,6 +43,7 @@ endchoice
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source "src/mainboard/gigabyte/ga_2761gxdk/Kconfig"
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source "src/mainboard/gigabyte/ga-6bxc/Kconfig"
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source "src/mainboard/gigabyte/ga-6bxe/Kconfig"
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source "src/mainboard/gigabyte/ga-b75m-d3h/Kconfig"
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source "src/mainboard/gigabyte/m57sli/Kconfig"
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source "src/mainboard/gigabyte/ma785gmt/Kconfig"
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source "src/mainboard/gigabyte/ma785gm/Kconfig"
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@ -0,0 +1,76 @@
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if BOARD_GIGABYTE_GA_B75M_D3H
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select ARCH_X86
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select CPU_INTEL_SOCKET_LGA1155
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select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
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select SOUTHBRIDGE_INTEL_C216
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select SUPERIO_ITE_IT8728F
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select HAVE_SMI_HANDLER
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select DYNAMIC_CBMEM
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select INTEL_INT15
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select VGA
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select INTEL_EDID
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select UDELAY_TSC
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select EARLY_CBMEM_INIT
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select SERIRQ_CONTINUOUS_MODE
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config DRAM_RESET_GATE_GPIO
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int
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default 25
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config USBDEBUG_HCD_INDEX
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int
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default 2
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config MAINBOARD_DIR
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string
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default gigabyte/ga-b75m-d3h
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config MAINBOARD_PART_NUMBER
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string
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default "GA-B75M-D3H"
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAX_CPUS
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int
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default 8
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config VGA_BIOS_ID
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string
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default "8086,0162"
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config VGA_BIOS_FILE
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string
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default "pci8086,0162.rom"
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config IFD_BIOS_SECTION
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string
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default "0x00600000:0x007fffff"
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config IFD_ME_SECTION
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string
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default "0x00001000:0x004fffff"
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endif # BOARD_GIGABYTE_GA_B75M_D3H
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
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romstage-y += gpio.c
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@ -0,0 +1,28 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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Scope (\_SB)
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{
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Device (PWRB)
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{
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Name (_HID, EisaId("PNP0C0C"))
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}
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}
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@ -0,0 +1,73 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, PICM)
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}
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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Return(Package(){0,0})
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}
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@ -0,0 +1,24 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* mainboard configuration */
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#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
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#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
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@ -0,0 +1,65 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// Thermal Zone
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Scope (\_TZ)
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{
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ThermalZone (THRM)
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{
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Name (_TC1, 0x02)
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Name (_TC2, 0x03)
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// Thermal zone polling frequency: 10 seconds
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Name (_TZP, 100)
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// Thermal sampling period for passive cooling: 10 seconds
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Name (_TSP, 100)
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// Convert from Degrees C to 1/10 Kelvin for ACPI
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Method (CTOK, 1)
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{
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// 10th of Degrees C
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Multiply (Arg0, 10, Local0)
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// Convert to Kelvin
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Add (Local0, 2732, Local0)
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Return (Local0)
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}
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// Threshold for OS to shutdown
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Method (_CRT, 0, Serialized)
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{
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Return (CTOK (\TCRT))
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}
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// Threshold for passive cooling
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Method (_PSV, 0, Serialized)
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{
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Return (CTOK (\TPSV))
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}
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// Processors used for passive cooling
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Method (_PSL, 0, Serialized)
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{
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Return (\PPKG ())
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}
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}
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}
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@ -0,0 +1 @@
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// Blank
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@ -0,0 +1,83 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <types.h>
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#include <string.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <arch/acpi.h>
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#include <arch/ioapic.h>
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#include <arch/acpigen.h>
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#include <arch/smp/mpspec.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/msr.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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memset((void *)gnvs, 0, sizeof(*gnvs));
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gnvs->apic = 1;
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gnvs->mpen = 1; /* Enable Multi Processing */
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gnvs->pcnt = dev_count_cpu();
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* IGD Displays */
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gnvs->ndid = 3;
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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// the lid is open by default.
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gnvs->lids = 1;
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acpi_update_thermal_table(gnvs);
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}
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unsigned long acpi_fill_slit(unsigned long current)
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{
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// Not implemented
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return current;
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}
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unsigned long acpi_fill_srat(unsigned long current)
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{
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/* No NUMA, no SRAT */
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return current;
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}
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@ -0,0 +1,6 @@
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Category: desktop
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Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=4150#sp
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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@ -0,0 +1,9 @@
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boot_option=Fallback
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last_boot=Fallback
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baud_rate=115200
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debug_level=Spew
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power_on_after_fail=Enable
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nmi=Enable
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volume=0x3
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sata_mode=AHCI
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hyper_threading=Enable
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|
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@ -0,0 +1,152 @@
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##
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## This file is part of the coreboot project.
|
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##
|
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## Copyright (C) 2007-2008 coresystems GmbH
|
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## Copyright (C) 2014 Vladimir Serbinenko
|
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##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
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|
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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||||
#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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||||
#56 8 r 0 day_of_month
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||||
#64 8 r 0 month
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#72 8 r 0 year
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||||
# -----------------------------------------------------------------
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# Status Register A
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||||
#80 4 r 0 rate_select
|
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#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
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||||
# -----------------------------------------------------------------
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||||
# Status Register B
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||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
|
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# -----------------------------------------------------------------
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||||
# Status Register C
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||||
#96 4 r 0 status_c_rsvd
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||||
#100 1 r 0 uf_flag
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||||
#101 1 r 0 af_flag
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||||
#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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||||
# -----------------------------------------------------------------
|
||||
# Status Register D
|
||||
#104 7 r 0 status_d_rsvd
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||||
#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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||||
# Diagnostic Status Register
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||||
#112 8 r 0 diag_rsvd1
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||||
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||||
# -----------------------------------------------------------------
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||||
0 120 r 0 reserved_memory
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||||
#120 264 r 0 unused
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
388 4 r 0 reboot_bits
|
||||
#390 2 r 0 unused?
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
# coreboot config options: console
|
||||
392 3 e 5 baud_rate
|
||||
395 4 e 6 debug_level
|
||||
#399 1 r 0 unused
|
||||
|
||||
400 8 h 0 volume
|
||||
|
||||
# coreboot config options: southbridge
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
#411 10 r 0 unused
|
||||
421 1 e 9 sata_mode
|
||||
#422 2 r 0 unused
|
||||
|
||||
# coreboot config options: cpu
|
||||
424 1 e 2 hyper_threading
|
||||
#425 7 r 0 unused
|
||||
|
||||
# coreboot config options: northbridge
|
||||
432 3 e 11 gfx_uma_size
|
||||
#435 549 r 0 unused
|
||||
|
||||
# SandyBridge MRC Scrambler Seed values
|
||||
896 32 r 0 mrc_scrambler_seed
|
||||
928 32 r 0 mrc_scrambler_seed_s3
|
||||
960 16 r 0 mrc_scrambler_seed_chk
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 1 Emergency
|
||||
6 2 Alert
|
||||
6 3 Critical
|
||||
6 4 Error
|
||||
6 5 Warning
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
9 0 AHCI
|
||||
9 1 IDE
|
||||
11 0 32M
|
||||
11 1 64M
|
||||
11 2 96M
|
||||
11 3 128M
|
||||
11 4 160M
|
||||
11 5 192M
|
||||
11 6 224M
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
checksum 392 415 984
|
||||
|
|
@ -0,0 +1,117 @@
|
|||
chip northbridge/intel/sandybridge
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_LGA1155
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/model_206ax
|
||||
register "pstate_coord_type" = "0xfe"
|
||||
register "c1_acpower" = "1"
|
||||
register "c2_acpower" = "3"
|
||||
register "c3_acpower" = "5"
|
||||
register "c1_battery" = "1"
|
||||
register "c2_battery" = "3"
|
||||
register "c3_battery" = "5"
|
||||
# Magic APIC ID to locate this chip
|
||||
device lapic 0xACAC off end
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1458 0x5000 inherit
|
||||
device pci 00.0 on # host bridge
|
||||
subsystemid 0x1458 0x5000
|
||||
end
|
||||
device pci 01.0 off end # PCIe Bridge for discrete graphics
|
||||
device pci 02.0 on # vga controller
|
||||
subsystemid 0x1458 0xd000
|
||||
end
|
||||
|
||||
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
|
||||
|
||||
# GPI routing
|
||||
register "alt_gp_smi_en" = "0x0000"
|
||||
register "gen1_dec" = "0x003c0a01"
|
||||
|
||||
# Set max SATA speed to 6.0 Gb/s
|
||||
register "sata_port_map" = "0x3f"
|
||||
register "sata_interface_speed_support" = "0x3"
|
||||
|
||||
register "pcie_port_coalesce" = "0"
|
||||
register "p_cnt_throttling_supported" = "0"
|
||||
register "docking_supported" = "0"
|
||||
register "sata_port_map" = "0x3f"
|
||||
register "c2_latency" = "0x0065"
|
||||
|
||||
device pci 14.0 on # USB 3.0 Controller
|
||||
subsystemid 0x1458 0x5007
|
||||
end
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 19.0 off end # Intel Gigabit Ethernet
|
||||
device pci 1a.0 on # USB2 EHCI #2
|
||||
subsystemid 0x1458 0x5006
|
||||
end
|
||||
device pci 1b.0 on # High Definition Audio
|
||||
subsystemid 0x1458 0xa002
|
||||
end
|
||||
device pci 1c.0 off end # PCIe Port #1
|
||||
device pci 1c.1 off end # PCIe Port #2
|
||||
device pci 1c.2 off end # PCIe Port #3
|
||||
device pci 1c.3 off end # PCIe Port #4
|
||||
device pci 1c.4 on # PCIe Port #5
|
||||
device pci 00.0 on # PCI 10ec:8168
|
||||
subsystemid 0x1458 0xe000
|
||||
end
|
||||
end
|
||||
device pci 1c.5 off end # PCIe Port #6
|
||||
device pci 1c.6 off end # PCIe Port #7
|
||||
device pci 1c.7 off end # PCIe Port #8
|
||||
device pci 1d.0 on # USB2 EHCI #1
|
||||
subsystemid 0x1458 0x5006
|
||||
end
|
||||
device pci 1e.0 on end # PCI bridge
|
||||
device pci 1f.0 on # ISA/LPC bridge
|
||||
subsystemid 0x1458 0x5001
|
||||
chip superio/ite/it8728f
|
||||
device pnp 2e.0 off end # FDC
|
||||
device pnp 2e.1 on # Serial Port 1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.2 on
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.3 on
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
drq 0x74 = 4
|
||||
end
|
||||
device pnp 2e.4 on # EC
|
||||
irq 0x70 = 9
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.6 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
irq 0x70 = 0
|
||||
end
|
||||
device pnp 2e.a off end # IR
|
||||
end
|
||||
end
|
||||
device pci 1f.2 on # SATA Controller 1
|
||||
subsystemid 0x1458 0xb005
|
||||
end
|
||||
device pci 1f.3 on # SMBus
|
||||
subsystemid 0x1458 0x5001
|
||||
end
|
||||
device pci 1f.4 off end
|
||||
device pci 1f.5 off end # SATA Controller 2
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x03, // DSDT revision: ACPI v3.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20141018 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||
/* global NVS and variables. */
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,433 @@
|
|||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_NATIVE,
|
||||
.gpio1 = GPIO_MODE_NATIVE,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_NATIVE,
|
||||
.gpio7 = GPIO_MODE_NATIVE,
|
||||
.gpio8 = GPIO_MODE_NATIVE,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_NATIVE,
|
||||
.gpio12 = GPIO_MODE_GPIO,
|
||||
.gpio13 = GPIO_MODE_NATIVE,
|
||||
.gpio14 = GPIO_MODE_NATIVE,
|
||||
.gpio15 = GPIO_MODE_NATIVE,
|
||||
.gpio16 = GPIO_MODE_NATIVE,
|
||||
.gpio17 = GPIO_MODE_NATIVE,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_NATIVE,
|
||||
.gpio22 = GPIO_MODE_NATIVE,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_NATIVE,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_NATIVE,
|
||||
.gpio28 = GPIO_MODE_NATIVE,
|
||||
.gpio29 = GPIO_MODE_NATIVE,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_OUTPUT,
|
||||
.gpio1 = GPIO_DIR_OUTPUT,
|
||||
.gpio2 = GPIO_DIR_OUTPUT,
|
||||
.gpio3 = GPIO_DIR_OUTPUT,
|
||||
.gpio4 = GPIO_DIR_OUTPUT,
|
||||
.gpio5 = GPIO_DIR_OUTPUT,
|
||||
.gpio6 = GPIO_DIR_OUTPUT,
|
||||
.gpio7 = GPIO_DIR_OUTPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio9 = GPIO_DIR_OUTPUT,
|
||||
.gpio10 = GPIO_DIR_OUTPUT,
|
||||
.gpio11 = GPIO_DIR_OUTPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_OUTPUT,
|
||||
.gpio14 = GPIO_DIR_OUTPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_OUTPUT,
|
||||
.gpio17 = GPIO_DIR_OUTPUT,
|
||||
.gpio18 = GPIO_DIR_OUTPUT,
|
||||
.gpio19 = GPIO_DIR_OUTPUT,
|
||||
.gpio20 = GPIO_DIR_OUTPUT,
|
||||
.gpio21 = GPIO_DIR_OUTPUT,
|
||||
.gpio22 = GPIO_DIR_OUTPUT,
|
||||
.gpio23 = GPIO_DIR_OUTPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio25 = GPIO_DIR_OUTPUT,
|
||||
.gpio26 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio30 = GPIO_DIR_INPUT,
|
||||
.gpio31 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio0 = GPIO_LEVEL_HIGH,
|
||||
.gpio1 = GPIO_LEVEL_HIGH,
|
||||
.gpio2 = GPIO_LEVEL_HIGH,
|
||||
.gpio3 = GPIO_LEVEL_HIGH,
|
||||
.gpio4 = GPIO_LEVEL_HIGH,
|
||||
.gpio5 = GPIO_LEVEL_HIGH,
|
||||
.gpio6 = GPIO_LEVEL_HIGH,
|
||||
.gpio7 = GPIO_LEVEL_HIGH,
|
||||
.gpio8 = GPIO_LEVEL_LOW,
|
||||
.gpio9 = GPIO_LEVEL_HIGH,
|
||||
.gpio10 = GPIO_LEVEL_HIGH,
|
||||
.gpio11 = GPIO_LEVEL_HIGH,
|
||||
.gpio12 = GPIO_LEVEL_HIGH,
|
||||
.gpio13 = GPIO_LEVEL_HIGH,
|
||||
.gpio14 = GPIO_LEVEL_HIGH,
|
||||
.gpio15 = GPIO_LEVEL_LOW,
|
||||
.gpio16 = GPIO_LEVEL_HIGH,
|
||||
.gpio17 = GPIO_LEVEL_HIGH,
|
||||
.gpio18 = GPIO_LEVEL_HIGH,
|
||||
.gpio19 = GPIO_LEVEL_LOW,
|
||||
.gpio20 = GPIO_LEVEL_LOW,
|
||||
.gpio21 = GPIO_LEVEL_LOW,
|
||||
.gpio22 = GPIO_LEVEL_LOW,
|
||||
.gpio23 = GPIO_LEVEL_LOW,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio25 = GPIO_LEVEL_HIGH,
|
||||
.gpio26 = GPIO_LEVEL_LOW,
|
||||
.gpio27 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
.gpio30 = GPIO_LEVEL_HIGH,
|
||||
.gpio31 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
.gpio0 = GPIO_RESET_PWROK,
|
||||
.gpio1 = GPIO_RESET_PWROK,
|
||||
.gpio2 = GPIO_RESET_PWROK,
|
||||
.gpio3 = GPIO_RESET_PWROK,
|
||||
.gpio4 = GPIO_RESET_PWROK,
|
||||
.gpio5 = GPIO_RESET_PWROK,
|
||||
.gpio6 = GPIO_RESET_PWROK,
|
||||
.gpio7 = GPIO_RESET_PWROK,
|
||||
.gpio8 = GPIO_RESET_PWROK,
|
||||
.gpio9 = GPIO_RESET_PWROK,
|
||||
.gpio10 = GPIO_RESET_PWROK,
|
||||
.gpio11 = GPIO_RESET_PWROK,
|
||||
.gpio12 = GPIO_RESET_PWROK,
|
||||
.gpio13 = GPIO_RESET_PWROK,
|
||||
.gpio14 = GPIO_RESET_PWROK,
|
||||
.gpio15 = GPIO_RESET_PWROK,
|
||||
.gpio16 = GPIO_RESET_PWROK,
|
||||
.gpio17 = GPIO_RESET_PWROK,
|
||||
.gpio18 = GPIO_RESET_PWROK,
|
||||
.gpio19 = GPIO_RESET_PWROK,
|
||||
.gpio20 = GPIO_RESET_PWROK,
|
||||
.gpio21 = GPIO_RESET_PWROK,
|
||||
.gpio22 = GPIO_RESET_PWROK,
|
||||
.gpio23 = GPIO_RESET_PWROK,
|
||||
.gpio24 = GPIO_RESET_RSMRST,
|
||||
.gpio25 = GPIO_RESET_PWROK,
|
||||
.gpio26 = GPIO_RESET_PWROK,
|
||||
.gpio27 = GPIO_RESET_PWROK,
|
||||
.gpio28 = GPIO_RESET_PWROK,
|
||||
.gpio29 = GPIO_RESET_PWROK,
|
||||
.gpio30 = GPIO_RESET_PWROK,
|
||||
.gpio31 = GPIO_RESET_PWROK,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio0 = GPIO_NO_INVERT,
|
||||
.gpio1 = GPIO_NO_INVERT,
|
||||
.gpio2 = GPIO_NO_INVERT,
|
||||
.gpio3 = GPIO_NO_INVERT,
|
||||
.gpio4 = GPIO_NO_INVERT,
|
||||
.gpio5 = GPIO_NO_INVERT,
|
||||
.gpio6 = GPIO_NO_INVERT,
|
||||
.gpio7 = GPIO_NO_INVERT,
|
||||
.gpio8 = GPIO_NO_INVERT,
|
||||
.gpio9 = GPIO_NO_INVERT,
|
||||
.gpio10 = GPIO_NO_INVERT,
|
||||
.gpio11 = GPIO_NO_INVERT,
|
||||
.gpio12 = GPIO_NO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
.gpio14 = GPIO_NO_INVERT,
|
||||
.gpio15 = GPIO_NO_INVERT,
|
||||
.gpio16 = GPIO_NO_INVERT,
|
||||
.gpio17 = GPIO_NO_INVERT,
|
||||
.gpio18 = GPIO_NO_INVERT,
|
||||
.gpio19 = GPIO_NO_INVERT,
|
||||
.gpio20 = GPIO_NO_INVERT,
|
||||
.gpio21 = GPIO_NO_INVERT,
|
||||
.gpio22 = GPIO_NO_INVERT,
|
||||
.gpio23 = GPIO_NO_INVERT,
|
||||
.gpio24 = GPIO_NO_INVERT,
|
||||
.gpio25 = GPIO_NO_INVERT,
|
||||
.gpio26 = GPIO_NO_INVERT,
|
||||
.gpio27 = GPIO_NO_INVERT,
|
||||
.gpio28 = GPIO_NO_INVERT,
|
||||
.gpio29 = GPIO_NO_INVERT,
|
||||
.gpio30 = GPIO_NO_INVERT,
|
||||
.gpio31 = GPIO_NO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
.gpio0 = GPIO_NO_BLINK,
|
||||
.gpio1 = GPIO_NO_BLINK,
|
||||
.gpio2 = GPIO_NO_BLINK,
|
||||
.gpio3 = GPIO_NO_BLINK,
|
||||
.gpio4 = GPIO_NO_BLINK,
|
||||
.gpio5 = GPIO_NO_BLINK,
|
||||
.gpio6 = GPIO_NO_BLINK,
|
||||
.gpio7 = GPIO_NO_BLINK,
|
||||
.gpio8 = GPIO_NO_BLINK,
|
||||
.gpio9 = GPIO_NO_BLINK,
|
||||
.gpio10 = GPIO_NO_BLINK,
|
||||
.gpio11 = GPIO_NO_BLINK,
|
||||
.gpio12 = GPIO_NO_BLINK,
|
||||
.gpio13 = GPIO_NO_BLINK,
|
||||
.gpio14 = GPIO_NO_BLINK,
|
||||
.gpio15 = GPIO_NO_BLINK,
|
||||
.gpio16 = GPIO_NO_BLINK,
|
||||
.gpio17 = GPIO_NO_BLINK,
|
||||
.gpio18 = GPIO_BLINK,
|
||||
.gpio19 = GPIO_NO_BLINK,
|
||||
.gpio20 = GPIO_NO_BLINK,
|
||||
.gpio21 = GPIO_NO_BLINK,
|
||||
.gpio22 = GPIO_NO_BLINK,
|
||||
.gpio23 = GPIO_NO_BLINK,
|
||||
.gpio24 = GPIO_NO_BLINK,
|
||||
.gpio25 = GPIO_NO_BLINK,
|
||||
.gpio26 = GPIO_NO_BLINK,
|
||||
.gpio27 = GPIO_NO_BLINK,
|
||||
.gpio28 = GPIO_NO_BLINK,
|
||||
.gpio29 = GPIO_NO_BLINK,
|
||||
.gpio30 = GPIO_NO_BLINK,
|
||||
.gpio31 = GPIO_NO_BLINK,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_NATIVE,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_NATIVE,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_OUTPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio40 = GPIO_DIR_INPUT,
|
||||
.gpio41 = GPIO_DIR_INPUT,
|
||||
.gpio42 = GPIO_DIR_INPUT,
|
||||
.gpio43 = GPIO_DIR_INPUT,
|
||||
.gpio44 = GPIO_DIR_INPUT,
|
||||
.gpio45 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio47 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_INPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_INPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio55 = GPIO_DIR_OUTPUT,
|
||||
.gpio56 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio58 = GPIO_DIR_INPUT,
|
||||
.gpio59 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_INPUT,
|
||||
.gpio61 = GPIO_DIR_OUTPUT,
|
||||
.gpio62 = GPIO_DIR_OUTPUT,
|
||||
.gpio63 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_LOW,
|
||||
.gpio33 = GPIO_LEVEL_LOW,
|
||||
.gpio34 = GPIO_LEVEL_LOW,
|
||||
.gpio35 = GPIO_LEVEL_LOW,
|
||||
.gpio36 = GPIO_LEVEL_LOW,
|
||||
.gpio37 = GPIO_LEVEL_LOW,
|
||||
.gpio38 = GPIO_LEVEL_HIGH,
|
||||
.gpio39 = GPIO_LEVEL_HIGH,
|
||||
.gpio40 = GPIO_LEVEL_HIGH,
|
||||
.gpio41 = GPIO_LEVEL_HIGH,
|
||||
.gpio42 = GPIO_LEVEL_HIGH,
|
||||
.gpio43 = GPIO_LEVEL_HIGH,
|
||||
.gpio44 = GPIO_LEVEL_HIGH,
|
||||
.gpio45 = GPIO_LEVEL_HIGH,
|
||||
.gpio46 = GPIO_LEVEL_HIGH,
|
||||
.gpio47 = GPIO_LEVEL_LOW,
|
||||
.gpio48 = GPIO_LEVEL_HIGH,
|
||||
.gpio49 = GPIO_LEVEL_LOW,
|
||||
.gpio50 = GPIO_LEVEL_HIGH,
|
||||
.gpio51 = GPIO_LEVEL_LOW,
|
||||
.gpio52 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_LOW,
|
||||
.gpio54 = GPIO_LEVEL_HIGH,
|
||||
.gpio55 = GPIO_LEVEL_LOW,
|
||||
.gpio56 = GPIO_LEVEL_LOW,
|
||||
.gpio57 = GPIO_LEVEL_HIGH,
|
||||
.gpio58 = GPIO_LEVEL_HIGH,
|
||||
.gpio59 = GPIO_LEVEL_HIGH,
|
||||
.gpio60 = GPIO_LEVEL_HIGH,
|
||||
.gpio61 = GPIO_LEVEL_LOW,
|
||||
.gpio62 = GPIO_LEVEL_HIGH,
|
||||
.gpio63 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
.gpio32 = GPIO_RESET_PWROK,
|
||||
.gpio33 = GPIO_RESET_PWROK,
|
||||
.gpio34 = GPIO_RESET_PWROK,
|
||||
.gpio35 = GPIO_RESET_PWROK,
|
||||
.gpio36 = GPIO_RESET_PWROK,
|
||||
.gpio37 = GPIO_RESET_PWROK,
|
||||
.gpio38 = GPIO_RESET_PWROK,
|
||||
.gpio39 = GPIO_RESET_PWROK,
|
||||
.gpio40 = GPIO_RESET_PWROK,
|
||||
.gpio41 = GPIO_RESET_PWROK,
|
||||
.gpio42 = GPIO_RESET_PWROK,
|
||||
.gpio43 = GPIO_RESET_PWROK,
|
||||
.gpio44 = GPIO_RESET_PWROK,
|
||||
.gpio45 = GPIO_RESET_PWROK,
|
||||
.gpio46 = GPIO_RESET_PWROK,
|
||||
.gpio47 = GPIO_RESET_PWROK,
|
||||
.gpio48 = GPIO_RESET_PWROK,
|
||||
.gpio49 = GPIO_RESET_PWROK,
|
||||
.gpio50 = GPIO_RESET_PWROK,
|
||||
.gpio51 = GPIO_RESET_PWROK,
|
||||
.gpio52 = GPIO_RESET_PWROK,
|
||||
.gpio53 = GPIO_RESET_PWROK,
|
||||
.gpio54 = GPIO_RESET_PWROK,
|
||||
.gpio55 = GPIO_RESET_PWROK,
|
||||
.gpio56 = GPIO_RESET_PWROK,
|
||||
.gpio57 = GPIO_RESET_PWROK,
|
||||
.gpio58 = GPIO_RESET_PWROK,
|
||||
.gpio59 = GPIO_RESET_PWROK,
|
||||
.gpio60 = GPIO_RESET_PWROK,
|
||||
.gpio61 = GPIO_RESET_PWROK,
|
||||
.gpio62 = GPIO_RESET_PWROK,
|
||||
.gpio63 = GPIO_RESET_PWROK,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio64 = GPIO_DIR_OUTPUT,
|
||||
.gpio65 = GPIO_DIR_OUTPUT,
|
||||
.gpio66 = GPIO_DIR_OUTPUT,
|
||||
.gpio67 = GPIO_DIR_OUTPUT,
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
.gpio73 = GPIO_DIR_INPUT,
|
||||
.gpio74 = GPIO_DIR_INPUT,
|
||||
.gpio75 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio64 = GPIO_LEVEL_HIGH,
|
||||
.gpio65 = GPIO_LEVEL_HIGH,
|
||||
.gpio66 = GPIO_LEVEL_HIGH,
|
||||
.gpio67 = GPIO_LEVEL_HIGH,
|
||||
.gpio68 = GPIO_LEVEL_HIGH,
|
||||
.gpio69 = GPIO_LEVEL_LOW,
|
||||
.gpio70 = GPIO_LEVEL_LOW,
|
||||
.gpio71 = GPIO_LEVEL_LOW,
|
||||
.gpio72 = GPIO_LEVEL_HIGH,
|
||||
.gpio73 = GPIO_LEVEL_LOW,
|
||||
.gpio74 = GPIO_LEVEL_HIGH,
|
||||
.gpio75 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
.gpio64 = GPIO_RESET_PWROK,
|
||||
.gpio65 = GPIO_RESET_PWROK,
|
||||
.gpio66 = GPIO_RESET_PWROK,
|
||||
.gpio67 = GPIO_RESET_PWROK,
|
||||
.gpio68 = GPIO_RESET_PWROK,
|
||||
.gpio69 = GPIO_RESET_PWROK,
|
||||
.gpio70 = GPIO_RESET_PWROK,
|
||||
.gpio71 = GPIO_RESET_PWROK,
|
||||
.gpio72 = GPIO_RESET_PWROK,
|
||||
.gpio73 = GPIO_RESET_PWROK,
|
||||
.gpio74 = GPIO_RESET_PWROK,
|
||||
.gpio75 = GPIO_RESET_PWROK,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,8 @@
|
|||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[0] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,106 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011-2012 Google Inc.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/interrupt.h>
|
||||
#include <boot/coreboot_tables.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <smbios.h>
|
||||
#include <device/pci.h>
|
||||
#include <cbfs.h>
|
||||
#include <build.h>
|
||||
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
const char *smbios_mainboard_bios_version(void)
|
||||
{
|
||||
/* Satisfy thinkpad_acpi. */
|
||||
if (strlen(CONFIG_LOCALVERSION))
|
||||
return "CBET4000 " CONFIG_LOCALVERSION;
|
||||
else
|
||||
return "CBET4000 " COREBOOT_VERSION;
|
||||
}
|
||||
|
||||
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
RCBA32(0x38c8) = 0x00002005;
|
||||
RCBA32(0x38c4) = 0x00802005;
|
||||
RCBA32(0x38c0) = 0x00000007;
|
||||
RCBA32(0x2240) = 0x00330e71;
|
||||
RCBA32(0x2244) = 0x003f0eb1;
|
||||
RCBA32(0x2248) = 0x002102cd;
|
||||
RCBA32(0x224c) = 0x00f60000;
|
||||
RCBA32(0x2250) = 0x00020000;
|
||||
RCBA32(0x2254) = 0x00e3004c;
|
||||
RCBA32(0x2258) = 0x00e20bef;
|
||||
RCBA32(0x2260) = 0x003304ed;
|
||||
RCBA32(0x2278) = 0x001107c1;
|
||||
RCBA32(0x227c) = 0x001d07e9;
|
||||
RCBA32(0x2280) = 0x00e20000;
|
||||
RCBA32(0x2284) = 0x00ee0000;
|
||||
RCBA32(0x2288) = 0x005b05d3;
|
||||
RCBA32(0x2318) = 0x04b8ff2e;
|
||||
RCBA32(0x231c) = 0x03930f2e;
|
||||
RCBA32(0x3808) = 0x005044a3;
|
||||
RCBA32(0x3810) = 0x52410000;
|
||||
RCBA32(0x3814) = 0x0000008a;
|
||||
RCBA32(0x3818) = 0x00000006;
|
||||
RCBA32(0x381c) = 0x0000072e;
|
||||
RCBA32(0x3820) = 0x0000000a;
|
||||
RCBA32(0x3824) = 0x00000123;
|
||||
RCBA32(0x3828) = 0x00000009;
|
||||
RCBA32(0x382c) = 0x00000001;
|
||||
RCBA32(0x3834) = 0x0000061a;
|
||||
RCBA32(0x3838) = 0x00000003;
|
||||
RCBA32(0x383c) = 0x00000a76;
|
||||
RCBA32(0x3840) = 0x00000004;
|
||||
RCBA32(0x3844) = 0x0000e5e4;
|
||||
RCBA32(0x3848) = 0x0000000e;
|
||||
}
|
||||
|
||||
// mainboard_enable is executed as first thing after
|
||||
// enumerate_buses().
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <pc80/mc146818rtc.h>
|
||||
#include <delay.h>
|
||||
#include <southbridge/intel/bd82x6x/nvs.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/bd82x6x/me.h>
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <cpu/intel/model_206ax/model_206ax.h>
|
||||
|
||||
/* The southbridge SMI handler checks whether gnvs has a
|
||||
* valid pointer before calling the trap handler
|
||||
*/
|
||||
extern global_nvs_t *gnvs;
|
||||
|
||||
static void mainboard_smm_init(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "initializing SMI\n");
|
||||
}
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
static int smm_initialized;
|
||||
|
||||
if (!smm_initialized) {
|
||||
mainboard_smm_init();
|
||||
smm_initialized = 1;
|
||||
}
|
||||
|
||||
/* On success, the IO Trap Handler returns 1
|
||||
* On failure, the IO Trap Handler returns a value != 1 */
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int mainboard_finalized = 0;
|
||||
|
||||
int mainboard_smi_apmc(u8 data)
|
||||
{
|
||||
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
|
||||
data);
|
||||
|
||||
if (!pmbase)
|
||||
return 0;
|
||||
|
||||
switch (data) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
break;
|
||||
case APM_CNT_FINALIZE:
|
||||
printk(BIOS_DEBUG, "APMC: FINALIZE\n");
|
||||
if (mainboard_finalized) {
|
||||
printk(BIOS_DEBUG, "APMC#: Already finalized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
intel_me_finalize_smm();
|
||||
intel_pch_finalize_smm();
|
||||
intel_sandybridge_finalize_smm();
|
||||
intel_model_206ax_finalize_smm();
|
||||
|
||||
mainboard_finalized = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2014 Damien Zammit <damien@zamaudio.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define SUPERIO_BASE 0x2e
|
||||
#define SUPERIO_DEV PNP_DEV(SUPERIO_BASE, 0)
|
||||
#define SUPERIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
|
||||
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <cpu/x86/lapic.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <console/console.h>
|
||||
#include <superio/ite/it8728f/it8728f.h>
|
||||
#include <superio/ite/common/ite.h>
|
||||
#include "northbridge/intel/sandybridge/sandybridge.h"
|
||||
#include "northbridge/intel/sandybridge/raminit_native.h"
|
||||
#include "southbridge/intel/bd82x6x/pch.h"
|
||||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
#include <arch/cpu.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
|
||||
static void it8728f_b75md3h_disable_reboot(device_t dev)
|
||||
{
|
||||
/* GPIO SIO settings */
|
||||
ite_reg_write(dev, 0xEF, 0x7E); // magic
|
||||
|
||||
ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
|
||||
ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
|
||||
ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
|
||||
ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
|
||||
ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
|
||||
ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
|
||||
ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
|
||||
ite_reg_write(dev, 0xe9, 0x27); // bus select disable
|
||||
ite_reg_write(dev, 0xf0, 0x10); // ?
|
||||
ite_reg_write(dev, 0xf1, 0x42); // ?
|
||||
ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
|
||||
|
||||
/* EC SIO settings */
|
||||
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
|
||||
ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
|
||||
ite_reg_write(IT8728F_EC, 0xf9, 0x48);
|
||||
ite_reg_write(IT8728F_EC, 0x60, 0x0a);
|
||||
ite_reg_write(IT8728F_EC, 0x61, 0x30);
|
||||
ite_reg_write(IT8728F_EC, 0x62, 0x0a);
|
||||
ite_reg_write(IT8728F_EC, 0x63, 0x20);
|
||||
ite_reg_write(IT8728F_EC, 0x30, 0x01);
|
||||
}
|
||||
|
||||
void rcba_config(void)
|
||||
{
|
||||
/*
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80);
|
||||
|
||||
outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
|
||||
|
||||
RCBA32(0x3500) = 0x2000035f;
|
||||
RCBA32(0x3504) = 0x2000035f;
|
||||
RCBA32(0x3508) = 0x2000035f;
|
||||
RCBA32(0x350c) = 0x2000035f;
|
||||
RCBA32(0x3510) = 0x2000035f;
|
||||
RCBA32(0x3514) = 0x2000035f;
|
||||
RCBA32(0x3518) = 0x2000035f;
|
||||
RCBA32(0x351c) = 0x2000035f;
|
||||
RCBA32(0x3520) = 0x2000035f;
|
||||
RCBA32(0x3524) = 0x2000035f;
|
||||
RCBA32(0x3528) = 0x2000035f;
|
||||
RCBA32(0x352c) = 0x2000035f;
|
||||
RCBA32(0x3530) = 0x2000035f;
|
||||
RCBA32(0x3534) = 0x2000035f;
|
||||
RCBA32(0x3560) = 0x024c8001;
|
||||
RCBA32(0x3564) = 0x000024a3;
|
||||
RCBA32(0x3568) = 0x00040002;
|
||||
RCBA32(0x356c) = 0x01000050;
|
||||
RCBA32(0x3570) = 0x02000662;
|
||||
RCBA32(0x3574) = 0x18000f9f;
|
||||
RCBA32(0x3578) = 0x1800ff4f;
|
||||
RCBA32(0x357c) = 0x0001d530;
|
||||
RCBA32(0x35a0) = 0xc0300c03;
|
||||
RCBA32(0x35a4) = 0x00241803;
|
||||
|
||||
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
|
||||
|
||||
outw (0x0000, DEFAULT_PMBASE | 0x003c);
|
||||
|
||||
RCBA32(0x2240) = 0x00330e71;
|
||||
RCBA32(0x2244) = 0x003f0eb1;
|
||||
RCBA32(0x2248) = 0x002102cd;
|
||||
RCBA32(0x224c) = 0x00f60000;
|
||||
RCBA32(0x2250) = 0x00020000;
|
||||
RCBA32(0x2254) = 0x00e3004c;
|
||||
RCBA32(0x2258) = 0x00e20bef;
|
||||
RCBA32(0x2260) = 0x003304ed;
|
||||
RCBA32(0x2278) = 0x001107c1;
|
||||
RCBA32(0x227c) = 0x001d07e9;
|
||||
RCBA32(0x2280) = 0x00e20000;
|
||||
RCBA32(0x2284) = 0x00ee0000;
|
||||
RCBA32(0x2288) = 0x005b05d3;
|
||||
RCBA32(0x2318) = 0x04b8ff2e;
|
||||
RCBA32(0x231c) = 0x03930f2e;
|
||||
// RCBA32(0x3418) = 0x1fee1fe1;
|
||||
RCBA32(0x3808) = 0x005044a3;
|
||||
RCBA32(0x3810) = 0x52410000;
|
||||
RCBA32(0x3814) = 0x0000008a;
|
||||
RCBA32(0x3818) = 0x00000006;
|
||||
RCBA32(0x381c) = 0x0000072e;
|
||||
RCBA32(0x3820) = 0x0000000a;
|
||||
RCBA32(0x3824) = 0x00000123;
|
||||
RCBA32(0x3828) = 0x00000009;
|
||||
RCBA32(0x382c) = 0x00000001;
|
||||
RCBA32(0x3834) = 0x0000061a;
|
||||
RCBA32(0x3838) = 0x00000003;
|
||||
RCBA32(0x383c) = 0x00000a76;
|
||||
RCBA32(0x3840) = 0x00000004;
|
||||
RCBA32(0x3844) = 0x0000e5e4;
|
||||
RCBA32(0x3848) = 0x0000000e;
|
||||
*/
|
||||
/* Disable unused devices (board specific) */
|
||||
RCBA32(FD) = 0x17ee1fe1;
|
||||
|
||||
/* Enable HECI */
|
||||
RCBA32(FD2) &= ~0x2;
|
||||
}
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
/*
|
||||
* Enable:
|
||||
* EC Decode Range PortA30/A20
|
||||
* SuperIO Port2E/2F
|
||||
* PS/2 Keyboard/Mouse Port60/64
|
||||
* FDD Port3F0h-3F5h and Port3F7h
|
||||
*/
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
|
||||
CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
|
||||
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01);
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
|
||||
|
||||
pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000);
|
||||
|
||||
/* Initialize SuperIO */
|
||||
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
it8728f_b75md3h_disable_reboot(SUPERIO_GPIO);
|
||||
}
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 5, 0 },
|
||||
{ 1, 5, 0 },
|
||||
{ 1, 5, 1 },
|
||||
{ 1, 5, 1 },
|
||||
{ 1, 5, 2 },
|
||||
{ 1, 5, 2 },
|
||||
{ 1, 5, 3 },
|
||||
{ 1, 5, 3 },
|
||||
{ 1, 5, 4 },
|
||||
{ 1, 5, 4 },
|
||||
{ 1, 5, 6 },
|
||||
{ 1, 5, 5 },
|
||||
{ 1, 5, 5 },
|
||||
{ 1, 5, 6 },
|
||||
};
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd) {
|
||||
read_spd (&spd[0], 0x50);
|
||||
read_spd (&spd[1], 0x51);
|
||||
read_spd (&spd[2], 0x52);
|
||||
read_spd (&spd[3], 0x53);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void dmi_config(void)
|
||||
{
|
||||
DMIBAR32(0x0218) = 0x06aa0b0c;
|
||||
DMIBAR32(0x021c) = 0x0b0d0b0d;
|
||||
DMIBAR32(0x0300) = 0x0011028d;
|
||||
DMIBAR32(0x0304) = 0x002102cd;
|
||||
DMIBAR32(0x030c) = 0x007d004b;
|
||||
DMIBAR32(0x0310) = 0x007e004c;
|
||||
DMIBAR32(0x0318) = 0x002304ad;
|
||||
DMIBAR32(0x031c) = 0x003304ed;
|
||||
DMIBAR32(0x03b8) = 0x005c05a4;
|
||||
DMIBAR32(0x03bc) = 0x006c05e4;
|
||||
DMIBAR32(0x0530) = 0x41d3b000;
|
||||
DMIBAR32(0x0534) = 0x00019f80;
|
||||
DMIBAR32(0x0ba4) = 0x0000000d;
|
||||
DMIBAR32(0x0d80) = 0x1c9cfc0b;
|
||||
DMIBAR32(0x0e1c) = 0x20000000;
|
||||
DMIBAR32(0x0e2c) = 0x20000000;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef GAB75MD3H_THERMAL_H
|
||||
#define GAB75MD3H_THERMAL_H
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 100
|
||||
|
||||
/* Temperature which OS will throttle CPU */
|
||||
#define PASSIVE_TEMPERATURE 90
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue