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agesa fam15 northbridge: change lapic_id to accommodate two CPUs 

According to http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c;hb=HEAD#l273 line 273,
adjust apic id to accommodate two CPUs.
The Tyan S8226 has two CPU sockets, and the current code just finds one CPU's cores.
we adjust apic_id in cpu_bus_scan so as to find all CPUs.

Change-Id: Ib3263fc6f5508f744b81e8e388fde9ccd9b51851
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1498
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Siyuan Wang 2012-09-07 19:03:24 +08:00 committed by Marc Jones
parent 1fb49dfa5e
commit 128c7d7315
1 changed files with 1 additions and 2 deletions
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3
src/northbridge/amd/agesa/family15/northbridge.c
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@ -1047,7 +1047,6 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
for (j = 0; j <= siblings; j++ ) {
extern CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration;
u32 modules = TopologyConfiguration.PlatformNumberOfModules;
u32 lapicid_start = 0;
/*
@ -1071,7 +1070,7 @@ static u32 cpu_bus_scan(device_t dev, u32 max)
lapicid_start = (lapicid_start + 1) * core_max;
printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
}
u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
u32 apic_id = (i * core_max) + j + lapicid_start;
printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
i, j, apic_id);