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mb/google/dragonegg: Make WP_RO range align with winbond specification 

This patch ensures to make memory protected range between
01C00000h - 01FFFFFFh as per winbond spi datasheet
https://www.winbond.com/resource-files/w25q256jv%20spi%20revb%2009202016.pdf
section 7.1.15
 
BUG=none
BRANCH=none
TEST=build and boot dragonegg.

Change-Id: Ife451233f60ef680088babbc824bfc5a17078cb9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30551
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-12-31 16:14:46 +05:30
parent 9d75e87428
commit 12992f62c0
1 changed files with 6 additions and 4 deletions
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10
src/mainboard/google/dragonegg/chromeos.fmd
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@ -27,15 +27,17 @@ FLASH@0xfe000000 0x2000000 {
RW_VPD@0x28000 0x2000 RW_VPD@0x28000 0x2000
RW_NVRAM@0x2a000 0x6000 RW_NVRAM@0x2a000 0x6000
} }
RW_LEGACY(CBFS)@0x5d0000 0x200000 RW_LEGACY(CBFS)@0x5d0000 0x230000
WP_RO@0x7d0000 0x430000 { # Make WP_RO region align with SPI vendor
# memory protected range specification.
WP_RO@0x800000 0x400000 {
RO_VPD@0x0 0x4000 RO_VPD@0x0 0x4000
RO_SECTION@0x4000 0x42c000 { RO_SECTION@0x4000 0x3fc000 {
FMAP@0x0 0x800 FMAP@0x0 0x800
RO_FRID@0x800 0x40 RO_FRID@0x800 0x40
RO_FRID_PAD@0x840 0x7c0 RO_FRID_PAD@0x840 0x7c0
GBB@0x1000 0xef000 GBB@0x1000 0xef000
COREBOOT(CBFS)@0xf0000 0x33c000 COREBOOT(CBFS)@0xf0000 0x30c000
} }
} }
} }