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soc/mediatek/common: Add halt() after triggering wdt reset 

It's more reasonable to halt when we trigger watchdog reset because
the whole system should be reset afterwards.

BUG=b:222217317
TEST=build pass

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2022-03-11 16:40:20 +08:00 committed by Felix Held
parent a4cdb5b381
commit 129b8ae551
1 changed files with 21 additions and 11 deletions
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32
src/soc/mediatek/common/wdt.c
View File

@ -3,11 +3,31 @@
#include <arch/cache.h> #include <arch/cache.h>
#include <device/mmio.h> #include <device/mmio.h>
#include <console/console.h> #include <console/console.h>
#include <halt.h>
#include <soc/wdt.h> #include <soc/wdt.h>
#include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/chromeos.h>
__weak void mtk_wdt_clr_status(void) { /* do nothing */ } __weak void mtk_wdt_clr_status(void) { /* do nothing */ }
static inline void mtk_wdt_swreset(void)
{
/*
* We trigger a secondary reset by triggering WDT hardware to send the
* signal to EC.
* We do not use do_board_reset() to send the signal to EC which is
* controlled by software driver.
* Before triggering the secondary reset, clean the data cache so the
* logs in cbmem console (either in SRAM or DRAM) can be flushed.
*/
printk(BIOS_INFO, "%s() called!\n", __func__);
dcache_clean_all();
setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
halt();
}
int mtk_wdt_init(void) int mtk_wdt_init(void)
{ {
uint32_t wdt_sta; uint32_t wdt_sta;
@ -23,17 +43,7 @@ int mtk_wdt_init(void)
if (wdt_sta & MTK_WDT_STA_HW_RST) { if (wdt_sta & MTK_WDT_STA_HW_RST) {
printk(BIOS_INFO, "hardware watchdog\n"); printk(BIOS_INFO, "hardware watchdog\n");
mark_watchdog_tombstone(); mark_watchdog_tombstone();
mtk_wdt_swreset();
/*
* We trigger secondary reset by triggering WDT hardware to send signal to EC.
* We do not use do_board_reset() to send signal to EC
* which is controlled by software driver.
* Before triggering secondary reset, clean the data cache so the logs in cbmem
* console (either in SRAM or DRAM) can be flushed.
*/
dcache_clean_all();
setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY);
write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY);
} else if (wdt_sta & MTK_WDT_STA_SW_RST) } else if (wdt_sta & MTK_WDT_STA_SW_RST)
printk(BIOS_INFO, "normal software reboot\n"); printk(BIOS_INFO, "normal software reboot\n");
else if (wdt_sta & MTK_WDT_STA_SPM_RST) else if (wdt_sta & MTK_WDT_STA_SPM_RST)