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mb/google/nissa/var/craask: Disable SD card based on fw_config 

Use fw_config Bit 5 to control whether to disable SD card:
Bit 5 = 0 --> enable SD card
Bit 5 = 1 --> disable SD card

BUG=b:229048361
TEST=emerge-nissa coreboot

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5e92600564e2138e32a0d2e60259b9767516a4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65129
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tyler Wang 2022-06-14 18:08:06 +08:00 committed by Felix Held
parent 3c5a638e32
commit 129e6b7c09
2 changed files with 34 additions and 0 deletions
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15
src/mainboard/google/brya/variants/craask/fw_config.c
View File

@ -36,6 +36,15 @@ static const struct pad_config wfc_disable_pads[] = {
PAD_NC(GPP_R7, NONE),
};
static const struct pad_config sd_disable_pads[] = {
/* D8 : SD_CLKREQ_ODL */
PAD_NC(GPP_D8, NONE),
/* H12 : SD_PERST_L */
PAD_NC(GPP_H12, NONE),
/* H13 : EN_PP3300_SD_X */
PAD_NC(GPP_H13, NONE),
};
static void fw_config_handle(void *unused)
{
if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
@ -50,5 +59,11 @@ static void fw_config_handle(void *unused)
printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
gpio_configure_pads(wfc_disable_pads, ARRAY_SIZE(wfc_disable_pads));
}
if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
printk(BIOS_INFO, "Disable SD card GPIO pins.\n");
gpio_configure_pads(sd_disable_pads, ARRAY_SIZE(sd_disable_pads));
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);

19
src/mainboard/google/brya/variants/craask/overridetree.cb
View File

@ -13,6 +13,10 @@ fw_config
option STYLUS_ABSENT 0
option STYLUS_PRESENT 1
end
field SD_CARD 5
option SD_GL9750S 0
option SD_ABSENT 1
end
end
chip soc/intel/alderlake
@ -320,6 +324,21 @@ chip soc/intel/alderlake
device generic 0 on end
end
end
device ref pcie_rp7 on
# Enable SD Card PCIe 7 using clk 3
register "pch_pcie_rp[PCH_RP(7)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H12)"
register "srcclk_pin" = "3"
device generic 0 on end
end
probe SD_CARD SD_GL9750S
end
device ref pch_espi on
chip ec/google/chromeec
use conn0 as mux_conn[0]