southbridge/intel: Tidy up preprocessor and headers

Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/x86/smm/smmrelocate.S

@@ -14,9 +14,6 @@
  * GNU General Public License for more details.
  */
 
-// Make sure no stage 2 code is included:
-#define __PRE_RAM__
-
 // FIXME: Is this piece of code southbridge specific, or
 // can it be cleaned up so this include is not required?
 // It's needed right now because we get our DEFAULT_PMBASE from

src/southbridge/intel/bd82x6x/azalia.c

@@ -23,6 +23,8 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <device/azalia_device.h>
+
+#include "chip.h"
 #include "pch.h"
 
 #define HDA_ICII_REG 0x68

src/southbridge/intel/bd82x6x/lpc.c

@@ -32,6 +32,7 @@
 #include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <string.h>
+#include "chip.h"
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>

src/southbridge/intel/bd82x6x/me.h

@@ -238,17 +238,14 @@ typedef enum {
 /* Defined in me_status.c for both romstage and ramstage */
 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
 
-#ifdef __PRE_RAM__
 void intel_early_me_status(void);
 int intel_early_me_init(void);
 int intel_early_me_uma_size(void);
 int intel_early_me_init_done(u8 status);
-#endif
 
-#ifdef __SMM__
 void intel_me_finalize_smm(void);
 void intel_me8_finalize_smm(void);
-#endif
+
 typedef struct {
 	u32       major_version  : 16;
 	u32       minor_version  : 16;

src/southbridge/intel/bd82x6x/pch.c

@@ -24,9 +24,11 @@
 #include <device/pci.h>
 #endif
 #include <device/pci_ops.h>
-#include "pch.h"
 #include <string.h>
 
+#include "chip.h"
+#include "pch.h"
+
 int pch_silicon_revision(void)
 {
 	static int pch_revision_id = -1;

src/southbridge/intel/bd82x6x/pch.h

@@ -56,20 +56,19 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(__ASSEMBLER__)
-#if !defined(__PRE_RAM__)
-#if !defined(__SIMPLE_DEVICE__)
-#include "chip.h"
-void pch_enable(struct device *dev);
-#endif
+
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
 int pch_silicon_supported(int type, int rev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#else /* __PRE_RAM__ */
+
 void enable_smbus(void);
 void enable_usb_bar(void);
+
+#if ENV_ROMSTAGE
 int smbus_read_byte(unsigned device, unsigned address);
+#endif
+
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
 void southbridge_rcba_config(void);
@@ -87,14 +86,11 @@ struct southbridge_usb_port
 };
 
 #ifndef __ROMCC__
+void pch_enable(struct device *dev);
 extern const struct southbridge_usb_port mainboard_usb_ports[14];
 #endif
 
-void
-early_usb_init (const struct southbridge_usb_port *portmap);
-
-#endif
-#endif
+void early_usb_init(const struct southbridge_usb_port *portmap);
 
 /* PM I/O Space */
 #define UPRWC			0x3c

src/southbridge/intel/bd82x6x/pcie.c

@@ -22,6 +22,8 @@
 #include <device/pci_ids.h>
 #include <southbridge/intel/common/pciehp.h>
 #include <assert.h>
+
+#include "chip.h"
 #include "pch.h"
 
 static void pch_pcie_pm_early(struct device *dev)

src/southbridge/intel/bd82x6x/sata.c

@@ -24,6 +24,7 @@
 #include <acpi/sata.h>
 #include <types.h>
 
+#include "chip.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_bd82x6x_config config_t;

src/southbridge/intel/bd82x6x/usb_xhci.c

@@ -21,6 +21,7 @@
 #include "pch.h"
 #include <device/pci_ehci.h>
 #include <device/pci_ops.h>
+#include "chip.h"
 
 static void usb_xhci_init(struct device *dev)
 {

src/southbridge/intel/i82371eb/i82371eb.h

@@ -17,18 +17,22 @@
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
-#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
-#if !defined(__PRE_RAM__)
-#include <device/device.h>
-#include "chip.h"
+#if !defined(__ACPI__)
 
+#ifndef __ROMCC__
+#include <device/device.h>
 void i82371eb_enable(struct device *dev);
-void i82371eb_hard_reset(void);
-#else
-void enable_smbus(void);
-int smbus_read_byte(u8 device, u8 address);
-void enable_pm(void);
 #endif
+
+void i82371eb_hard_reset(void);
+
+void enable_smbus(void);
+void enable_pm(void);
+
+#if ENV_ROMSTAGE
+int smbus_read_byte(u8 device, u8 address);
+#endif
+
 #endif
 
 /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the

src/southbridge/intel/i82371eb/ide.c

@@ -22,6 +22,7 @@
 #include <device/pci.h>
 #include <device/pci_ops.h>
 #include <device/pci_ids.h>
+#include "chip.h"
 #include "i82371eb.h"
 
 /**

src/southbridge/intel/i82371eb/smbus.c

@@ -26,6 +26,7 @@
 #include <device/pci_ids.h>
 #include <device/smbus.h>
 #include <southbridge/intel/common/smbus.h>
+#include "chip.h"
 #include "i82371eb.h"
 
 static void pwrmgt_enable(struct device *dev)

src/southbridge/intel/i82801dx/ide.c

@@ -19,6 +19,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
+#include "chip.h"
 #include "i82801dx.h"
 
 typedef struct southbridge_intel_i82801dx_config config_t;

src/southbridge/intel/i82801dx/lpc.c

@@ -26,6 +26,7 @@
 #include <pc80/isa-dma.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
+#include "chip.h"
 #include "i82801dx.h"
 
 #define NMI_OFF 0

src/southbridge/intel/i82801gx/azalia.c

@@ -22,6 +22,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <device/azalia_device.h>
+#include "chip.h"
 #include "i82801gx.h"
 
 #define HDA_ICII_REG 0x68

src/southbridge/intel/i82801gx/i82801gx.h

@@ -34,13 +34,14 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(__ASSEMBLER__)
-#if !defined(__PRE_RAM__)
-#if !defined(__SIMPLE_DEVICE__)
+#ifndef __ROMCC__
+#include <device/device.h>
 void i82801gx_enable(struct device *dev);
 #endif
-#else
+
 void enable_smbus(void);
+
+#if ENV_ROMSTAGE
 int smbus_read_byte(unsigned int device, unsigned int address);
 int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
 		u8 *buf);
@@ -48,7 +49,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
 int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
 		const u8 *buf);
 #endif
-#endif
 
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1

src/southbridge/intel/i82801ix/hdaudio.c

@@ -23,6 +23,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <device/azalia_device.h>
+#include "chip.h"
 #include "i82801ix.h"
 
 #define HDA_ICII_REG 0x68

src/southbridge/intel/i82801ix/i82801ix.c

@@ -22,6 +22,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <console/console.h>
+#include "chip.h"
 #include "i82801ix.h"
 
 typedef struct southbridge_intel_i82801ix_config config_t;

src/southbridge/intel/i82801ix/i82801ix.h

@@ -18,12 +18,6 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H
 #define SOUTHBRIDGE_INTEL_I82801GX_I82801IX_H
 
-#ifndef __ACPI__
-#ifndef __ASSEMBLER__
-#include "chip.h"
-#endif
-#endif
-
 #define DEFAULT_TBAR		((u8 *)0xfed1b000)
 
 #include <southbridge/intel/common/rcba.h>
@@ -214,12 +208,13 @@ static inline int lpc_is_mobile(const u16 devid)
 
 void aseg_smm_lock(void);
 
-#if defined(__PRE_RAM__)
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
 void i82801ix_early_init(void);
 void i82801ix_dmi_setup(void);
 void i82801ix_dmi_poll_vc1(void);
+
+#if ENV_ROMSTAGE
+int smbus_read_byte(unsigned device, unsigned address);
 #endif
 
 #endif

src/southbridge/intel/i82801ix/lpc.c

@@ -30,6 +30,7 @@
 #include <arch/acpigen.h>
 #include <cbmem.h>
 #include <string.h>
+#include "chip.h"
 #include "i82801ix.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>

src/southbridge/intel/i82801ix/sata.c

@@ -25,6 +25,7 @@
 #include <pc80/mc146818rtc.h>
 #include <types.h>
 
+#include "chip.h"
 #include "i82801ix.h"
 
 typedef struct southbridge_intel_i82801ix_config config_t;

src/southbridge/intel/i82801jx/hdaudio.c

@@ -23,6 +23,7 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <device/azalia_device.h>
+#include "chip.h"
 #include "i82801jx.h"
 
 #define HDA_ICII_REG 0x68

src/southbridge/intel/i82801jx/i82801jx.c

@@ -22,6 +22,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <console/console.h>
+#include "chip.h"
 #include "i82801jx.h"
 
 typedef struct southbridge_intel_i82801jx_config config_t;

src/southbridge/intel/i82801jx/i82801jx.h

@@ -18,12 +18,6 @@
 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H
 #define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H
 
-#ifndef __ACPI__
-#ifndef __ASSEMBLER__
-#include "chip.h"
-#endif
-#endif
-
 #define DEFAULT_TBAR		((u8 *)0xfed1b000)
 
 #include <southbridge/intel/common/rcba.h>
@@ -222,7 +216,6 @@
 
 
 #ifndef __ACPI__
-#ifndef __ASSEMBLER__
 
 #include <device/pci_ops.h>
 
@@ -232,7 +225,7 @@ static inline int lpc_is_mobile(const u16 devid)
 }
 #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
 
-#if defined(__PRE_RAM__)
+#if ENV_ROMSTAGE
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
@@ -242,7 +235,6 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
 		const u8 *buf);
 #endif
 
-#endif
 #endif
 
 #endif

src/southbridge/intel/i82801jx/lpc.c

@@ -31,6 +31,7 @@
 #include <arch/smp/mpspec.h>
 #include <cbmem.h>
 #include <string.h>
+#include "chip.h"
 #include "i82801jx.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>

src/southbridge/intel/i82801jx/sata.c

@@ -25,6 +25,7 @@
 #include <pc80/mc146818rtc.h>
 #include <types.h>
 
+#include "chip.h"
 #include "i82801jx.h"
 
 typedef struct southbridge_intel_i82801jx_config config_t;

src/southbridge/intel/ibexpeak/lpc.c

@@ -34,6 +34,7 @@
 #include <cbmem.h>
 #include <string.h>
 #include <cpu/x86/smm.h>
+#include "chip.h"
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>

src/southbridge/intel/ibexpeak/me.h

@@ -239,17 +239,14 @@ typedef enum {
 /* Defined in me_status.c for both romstage and ramstage */
 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
 
-#ifdef __PRE_RAM__
 void intel_early_me_status(void);
 int intel_early_me_init(void);
 int intel_early_me_uma_size(void);
 int intel_early_me_init_done(u8 status);
-#endif
 
-#ifdef __SMM__
 void intel_me_finalize_smm(void);
 void intel_me8_finalize_smm(void);
-#endif
+
 typedef struct {
 	u32       major_version  : 16;
 	u32       minor_version  : 16;

src/southbridge/intel/ibexpeak/pch.h

@@ -51,29 +51,26 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(__ASSEMBLER__)
-#if !defined(__PRE_RAM__)
-#if !defined(__SIMPLE_DEVICE__)
-#include "chip.h"
-void pch_enable(struct device *dev);
-#endif
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
 int pch_silicon_supported(int type, int rev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if CONFIG(ELOG)
-void pch_log_state(void);
-#endif
-#else /* __PRE_RAM__ */
 void enable_smbus(void);
 void enable_usb_bar(void);
+
+#if ENV_ROMSTAGE
 int smbus_read_byte(unsigned device, unsigned address);
 int smbus_write_byte(unsigned device, unsigned address, u8 data);
 int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
 int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
+#endif
+
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
-#endif
+
+#ifndef __ROMCC__
+#include <device/device.h>
+void pch_enable(struct device *dev);
 #endif
 
 #define MAINBOARD_POWER_OFF	0

src/southbridge/intel/ibexpeak/sata.c

@@ -25,6 +25,7 @@
 #include <acpi/sata.h>
 #include <types.h>
 
+#include "chip.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_ibexpeak_config config_t;

src/southbridge/intel/lynxpoint/chip.h

@@ -117,6 +117,5 @@ struct southbridge_intel_lynxpoint_config {
 	bool docking_supported;
 };
 
-extern struct chip_operations southbridge_intel_lynxpoint_ops;
 
 #endif				/* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */

src/southbridge/intel/lynxpoint/lp_gpio.c

@@ -24,7 +24,7 @@
 
 static u16 get_gpio_base(void)
 {
-#if defined(__PRE_RAM__) || defined(__SMM__)
+#ifdef __SIMPLE_DEVICE__
 	return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
 #else
 	return pci_read_config16(pcidev_on_root(0x1f, 0),

src/southbridge/intel/lynxpoint/lpc.c

@@ -30,6 +30,7 @@
 #include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <string.h>
+#include "chip.h"
 #include "nvs.h"
 #include "pch.h"
 #include <arch/acpigen.h>

src/southbridge/intel/lynxpoint/me.h

@@ -326,17 +326,13 @@ typedef enum {
 /* Defined in me_status.c for both romstage and ramstage */
 void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2);
 
-#ifdef __PRE_RAM__
 void intel_early_me_status(void);
 int intel_early_me_init(void);
 int intel_early_me_uma_size(void);
 int intel_early_me_init_done(u8 status);
-#endif
 
-#ifdef __SMM__
 void intel_me_finalize_smm(void);
 void intel_me8_finalize_smm(void);
-#endif
 
 /*
  * ME to BIOS Payload Datastructures and definitions. The ordering of the

src/southbridge/intel/lynxpoint/me_9.x.c

@@ -35,6 +35,7 @@
 #include <elog.h>
 #include <halt.h>
 
+#include "chip.h"
 #include "me.h"
 #include "pch.h"
 

src/southbridge/intel/lynxpoint/pch.h

@@ -88,13 +88,10 @@
 
 #ifndef __ACPI__
 
-#if defined(__SMM__) && !defined(__ASSEMBLER__)
 void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 void usb_ehci_disable(pci_devfn_t dev);
 void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 void usb_xhci_route_all(void);
-#endif
-
 
 /* State Machine configuration. */
 #define RCBA_REG_SIZE_MASK 0x8000
@@ -135,7 +132,6 @@ struct rcba_config_instruction
 	u32 or_value;
 };
 
-#if !defined(__ASSEMBLER__)
 void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
 int pch_silicon_revision(void);
 int pch_silicon_id(void);
@@ -169,30 +165,26 @@ void disable_all_gpe(void);
 void enable_gpe(u32 mask);
 void disable_gpe(u32 mask);
 
-#if !defined(__PRE_RAM__) && !defined(__SMM__)
-#include <device/device.h>
-#include "chip.h"
 void pch_enable(struct device *dev);
 void pch_disable_devfn(struct device *dev);
 u32 pch_iobp_read(u32 address);
 void pch_iobp_write(u32 address, u32 data);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#if CONFIG(ELOG)
 void pch_log_state(void);
-#endif
 void acpi_create_intel_hpet(acpi_hpet_t * hpet);
 void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 
-#else
 void enable_smbus(void);
-void enable_usb_bar(void);
+
+#if ENV_ROMSTAGE
 int smbus_read_byte(unsigned device, unsigned address);
+#endif
+
+void enable_usb_bar(void);
 int early_pch_init(const void *gpio_map,
                    const struct rcba_config_instruction *rcba_config);
 void pch_enable_lpc(void);
 void mainboard_config_superio(void);
-#endif /* !__PRE_RAM__ && !__SMM__ */
-#endif /* __ASSEMBLER__ */
 
 #define MAINBOARD_POWER_OFF	0
 #define MAINBOARD_POWER_ON	1

src/southbridge/intel/lynxpoint/pcie.c

@@ -26,6 +26,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <stddef.h>
 #include <stdint.h>
+#include "chip.h"
 
 #define MAX_NUM_ROOT_PORTS 8
 

src/southbridge/intel/lynxpoint/sata.c

@@ -21,6 +21,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <delay.h>
+#include "chip.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_lynxpoint_config config_t;

src/southbridge/intel/lynxpoint/serialio.c

@@ -22,6 +22,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <stdlib.h>
+#include "chip.h"
 #include "pch.h"
 #include "nvs.h"
 

src/southbridge/intel/lynxpoint/usb_xhci.c

@@ -21,6 +21,7 @@
 #include <arch/io.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
+#include "chip.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_lynxpoint_config config_t;