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mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaks 

Contrary to mc_ehl2, which this variant is based on, this board
doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the
attempts to modify the bridge's registers unnecessary.

Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jan Samek 2022-12-16 13:21:11 +01:00 committed by Felix Held
parent 37cb922374
commit 12b2a3a477
1 changed files with 1 additions and 12 deletions
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13
src/mainboard/siemens/mc_ehl/variants/mc_ehl3/mainboard.c
View File

@ -2,12 +2,10 @@
#include <baseboard/variants.h>
#include <bootstate.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <gpio.h>
#include <intelblocks/pcr.h>
#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
#define HOSTCTRL2 0x3E
#define HOSTCTRL2_PRESET (1 << 15)
@ -22,15 +20,6 @@ void variant_mainboard_final(void)
{
struct device *dev;
/* PIR8 register mapping for PCIe root ports
INTA#->PIRQC#, INTB#->PIRQD#, INTC#->PIRQA#, INTD#-> PIRQB# */
pcr_write16(PID_ITSS, 0x3150, 0x1032);
/* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */
dev = dev_find_device(PCI_VID_TI, PCI_DID_TI_XIO2001, 0);
if (dev)
pci_write_config8(dev, 0xd8, 0x3e);
/* Limit SD-Card speed to DDR50 mode to avoid SDR104/SDR50 modes due to
layout limitations. */
dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);