From 12b835050f0af9341b257560b60a8060c8fad328 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 10 Mar 2020 17:50:28 -0700 Subject: [PATCH] soc/intel: Enable GPIO functions in verstage Enable GPIO functionality in verstage so platforms can read a PCH GPIO in verstage to determine recovery mode. BUG=b:151102807 TEST=make build successful Signed-off-by: Bora Guvendik Change-Id: I4e3b9da307dcf59ab251d8a6a5e09c2a3cfc59fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/39501 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 9d8fa6f692..e7169cff42 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -58,6 +58,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +verstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += gpio_tgl.c CPPFLAGS_common += -I$(src)/soc/intel/tigerlake CPPFLAGS_common += -I$(src)/soc/intel/tigerlake/include