s4880
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
7c8d35273f
commit
12d2e683f4
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@ -0,0 +1,221 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses MAINBOARD
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uses ARCH
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#
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#
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###
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### Set all of the defaults for an x86 architecture
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###
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#
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#
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###
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### Build the objects we have code for in this directory.
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###
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##object mainboard.o
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config chip.h
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#register "fixup_scsi" = "1"
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#register "fixup_vga" = "1"
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driver mainboard.o
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driver lsi_scsi.o
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#driver adaptec_scsi.o
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driver si_sata.o
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#driver intel_nic.o
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object reset.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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arch i386 end
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#cpu k8 end
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#
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###
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### Build our 16 bit and 32 bit linuxBIOS entry code
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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###
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### Build our reset vector (This is where linuxBIOS is entered)
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###
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if USE_FALLBACK_IMAGE
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mainboardinit cpu/i386/reset16.inc
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ldscript /cpu/i386/reset16.lds
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else
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mainboardinit cpu/i386/reset32.inc
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ldscript /cpu/i386/reset32.lds
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end
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#
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#### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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#
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###
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### Include an id string (For safe flashing)
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###
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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#
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####
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#### This is the early phase of linuxBIOS startup
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#### Things are delicate and we test to see if we should
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#### failover to another image.
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####
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#option MAX_REBOOT_CNT=2
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if USE_FALLBACK_IMAGE
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ldscript /arch/i386/lib/failover.lds
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end
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#
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###
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### Setup our mtrrs
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###
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mainboardinit cpu/k8/earlymtrr.inc
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###
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### Only the bootstrap cpu makes it here.
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### Failover if we need to
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###
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#
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if USE_FALLBACK_IMAGE
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mainboardinit ./failover.inc
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end
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#
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#
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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####
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#
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###
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### When debugging disable the watchdog timer
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###
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##option MAXIMUM_CONSOLE_LOGLEVEL=7
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#default MAXIMUM_CONSOLE_LOGLEVEL=7
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#
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#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
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#
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
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end
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makerule ./failover.inc
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depends "./romcc ./failover.E"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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end
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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mainboardinit cpu/k8/disable_mmx_sse.inc
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#
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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pci 0:18.0
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pci 0:18.1
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pci 0:18.2
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pci 0:18.3
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southbridge amd/amd8131 "amd8131" link 2
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pci 0:0.0
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pci 0:0.1
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pci 0:1.0
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pci 0:1.1
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end
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southbridge amd/amd8111 "amd8111" link 2
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pci 0:0.0
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pci 0:1.0 on
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pci 0:1.1 on
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pci 0:1.2 on
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pci 0:1.3 on
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pci 0:1.5 off
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pci 0:1.6 off
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pci 1:0.0 on
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 off
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end
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end
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northbridge amd/amdk8 "mc1"
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pci 0:19.0
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pci 0:19.0
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pci 0:19.0
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pci 0:19.1
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pci 0:19.2
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pci 0:19.3
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end
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northbridge amd/amdk8 "mc2"
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.0
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pci 0:1a.1
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pci 0:1a.2
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pci 0:1a.3
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end
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northbridge amd/amdk8 "mc3"
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.0
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pci 0:1b.1
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pci 0:1b.2
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pci 0:1b.3
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end
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#northbridge amd/amdk8
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#end
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#southbridge amd/amd8111 "amd8111"
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#end
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#southbridge amd/amd8131 "amd8131"
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#end
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#mainboardinit archi386/smp/secondary.inc
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#superio NSC/pc87360
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# register "com1" = "{1}"
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# register "lpt" = "{1}"
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#end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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#dir /bioscall
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#dir /cpu/k8
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cpu k8 "cpu0"
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register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
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end
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cpu k8 "cpu1"
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end
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cpu k8 "cpu2"
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end
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cpu k8 "cpu3"
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end
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@ -0,0 +1 @@
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2.0
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@ -0,0 +1,284 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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#include "lib/delay.c"
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#include "cpu/p6/boot_cpu.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#define REV_B_RESET 0
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static void memreset_setup(void)
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{
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#if REV_B_RESET==1
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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#else
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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#endif
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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udelay(800);
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#if REV_B_RESET==1
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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#endif
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udelay(90);
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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* i: 0, 1, 2, 3, 4, 5, 6, 7
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*
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* [ 0: 3] Request Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [11: 8] Response Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [19:16] Broadcast route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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*/
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uint32_t ret=0x00010101; /* default row entry */
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static const unsigned int rows_4p[4][4] = {
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{ 0x00070101, 0x00010202, 0x00030404, 0x00010204 },
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{ 0x00010202, 0x000b0101, 0x00010208, 0x00030808 },
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{ 0x00030808, 0x00010208, 0x000b0101, 0x00010202 },
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{ 0x00010204, 0x00030404, 0x00010202, 0x00070101 }
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};
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if (!(node>=maxnodes || row>=maxnodes)) {
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ret=rows_4p[node][row];
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}
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return ret;
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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#define SMBUS_HUB 0x18
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unsigned device=(ctrl->channel0[0])>>8;
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smbus_write_byte(SMBUS_HUB , 0x01, device);
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smbus_write_byte(SMBUS_HUB , 0x03, 0);
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}
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#if 0
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static inline void change_i2c_mux(unsigned device)
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{
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#define SMBUS_HUB 0x18
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smbus_write_byte(SMBUS_HUB , 0x01, device);
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smbus_write_byte(SMBUS_HUB , 0x03, 0);
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}
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#endif
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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||||||
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/* include mainboard specific ht code */
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#include "hypertransport.c"
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//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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||||||
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||||||
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#include "resourcemap.c" /* tyan does not want the default */
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||||||
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static void enable_lapic(void)
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||||||
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{
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msr_t msr;
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||||||
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msr = rdmsr(0x1b);
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||||||
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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||||||
|
msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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||||||
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}
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||||||
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||||||
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static void stop_this_cpu(void)
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||||||
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{
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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||||||
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||||||
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/* If I haven't halted spin forever */
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||||||
|
for(;;) {
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||||||
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hlt();
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||||||
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}
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||||||
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}
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||||||
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#define FIRST_CPU 1
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||||||
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#define SECOND_CPU 1
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||||||
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||||||
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#define THIRD_CPU 1
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||||||
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#define FOURTH_CPU 1
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||||||
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||||||
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU + THIRD_CPU + FOURTH_CPU)
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||||||
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|
||||||
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#define RC0 ((1<<1)<<8)
|
||||||
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#define RC1 ((1<<2)<<8)
|
||||||
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#define RC2 ((1<<3)<<8)
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||||||
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#define RC3 ((1<<4)<<8)
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||||||
|
|
||||||
|
#define DIMM0 0x50
|
||||||
|
#define DIMM1 0x51
|
||||||
|
#define DIMM2 0x52
|
||||||
|
#define DIMM3 0x53
|
||||||
|
|
||||||
|
static void main(void)
|
||||||
|
{
|
||||||
|
static const struct mem_controller cpu[] = {
|
||||||
|
#if FIRST_CPU
|
||||||
|
{
|
||||||
|
.node_id = 0,
|
||||||
|
.f0 = PCI_DEV(0, 0x18, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x18, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x18, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x18, 3),
|
||||||
|
.channel0 = { RC0|DIMM0, RC0|DIMM2, 0, 0 },
|
||||||
|
.channel1 = { RC0|DIMM1, RC0|DIMM3, 0, 0 },
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if SECOND_CPU
|
||||||
|
{
|
||||||
|
.node_id = 1,
|
||||||
|
.f0 = PCI_DEV(0, 0x19, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x19, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x19, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x19, 3),
|
||||||
|
.channel0 = { RC1|DIMM0, 0 , 0, 0 },
|
||||||
|
.channel1 = { RC1|DIMM1, 0, 0, 0 },
|
||||||
|
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if THIRD_CPU
|
||||||
|
{
|
||||||
|
.node_id = 2,
|
||||||
|
.f0 = PCI_DEV(0, 0x1a, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x1a, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x1a, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x1a, 3),
|
||||||
|
.channel0 = { RC2|DIMM0, 0, 0, 0 },
|
||||||
|
.channel1 = { RC2|DIMM1, 0, 0, 0 },
|
||||||
|
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
#if FOURTH_CPU
|
||||||
|
{
|
||||||
|
.node_id = 3,
|
||||||
|
.f0 = PCI_DEV(0, 0x1b, 0),
|
||||||
|
.f1 = PCI_DEV(0, 0x1b, 1),
|
||||||
|
.f2 = PCI_DEV(0, 0x1b, 2),
|
||||||
|
.f3 = PCI_DEV(0, 0x1b, 3),
|
||||||
|
.channel0 = { RC3|DIMM0, 0, 0, 0 },
|
||||||
|
.channel1 = { RC3|DIMM1, 0, 0, 0 },
|
||||||
|
|
||||||
|
},
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
int i;
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
enable_lapic();
|
||||||
|
init_timer();
|
||||||
|
if (!boot_cpu() ) {
|
||||||
|
// notify_bsp_ap_is_stopped();
|
||||||
|
stop_this_cpu();
|
||||||
|
}
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
setup_s4880_resource_map();
|
||||||
|
setup_coherent_ht_domain();
|
||||||
|
enumerate_ht_chain(0);
|
||||||
|
distinguish_cpu_resets(0);
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
dump_pci_devices();
|
||||||
|
#endif
|
||||||
|
enable_smbus();
|
||||||
|
#if 0
|
||||||
|
|
||||||
|
// activate_spd_rom(&cpu[0]);
|
||||||
|
// dump_spd_registers(&cpu[0]);
|
||||||
|
|
||||||
|
// for(i=0;i<4;i++) {
|
||||||
|
// activate_spd_rom(&cpu[i]);
|
||||||
|
// dump_smbus_registers();
|
||||||
|
// }
|
||||||
|
for(i=1;i<256;i=i*2) {
|
||||||
|
change_i2c_mux(i);
|
||||||
|
dump_smbus_registers();
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
memreset_setup();
|
||||||
|
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
dump_pci_devices();
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
dump_pci_device(PCI_DEV(0, 0x18, 1));
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Check all of memory */
|
||||||
|
#if 0
|
||||||
|
msr_t msr;
|
||||||
|
msr = rdmsr(TOP_MEM2);
|
||||||
|
print_debug("TOP_MEM2: ");
|
||||||
|
print_debug_hex32(msr.hi);
|
||||||
|
print_debug_hex32(msr.lo);
|
||||||
|
print_debug("\r\n");
|
||||||
|
#endif
|
||||||
|
/*
|
||||||
|
#if 0
|
||||||
|
ram_check(0x00000000, msr.lo+(msr.hi<<32));
|
||||||
|
#else
|
||||||
|
#if TOTAL_CPUS < 2
|
||||||
|
// Check 16MB of memory @ 0
|
||||||
|
ram_check(0x00000000, 0x01000000);
|
||||||
|
#else
|
||||||
|
// Check 16MB of memory @ 2GB
|
||||||
|
ram_check(0x80000000, 0x81000000);
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
*/
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,6 @@
|
||||||
|
extern struct chip_control mainboard_tyan_s4880_control;
|
||||||
|
|
||||||
|
struct mainboard_tyan_s4880_config {
|
||||||
|
// int fixup_scsi;
|
||||||
|
// int fixup_vga;
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,74 @@
|
||||||
|
entries
|
||||||
|
|
||||||
|
#start-bit length config config-ID name
|
||||||
|
#0 8 r 0 seconds
|
||||||
|
#8 8 r 0 alarm_seconds
|
||||||
|
#16 8 r 0 minutes
|
||||||
|
#24 8 r 0 alarm_minutes
|
||||||
|
#32 8 r 0 hours
|
||||||
|
#40 8 r 0 alarm_hours
|
||||||
|
#48 8 r 0 day_of_week
|
||||||
|
#56 8 r 0 day_of_month
|
||||||
|
#64 8 r 0 month
|
||||||
|
#72 8 r 0 year
|
||||||
|
#80 4 r 0 rate_select
|
||||||
|
#84 3 r 0 REF_Clock
|
||||||
|
#87 1 r 0 UIP
|
||||||
|
#88 1 r 0 auto_switch_DST
|
||||||
|
#89 1 r 0 24_hour_mode
|
||||||
|
#90 1 r 0 binary_values_enable
|
||||||
|
#91 1 r 0 square-wave_out_enable
|
||||||
|
#92 1 r 0 update_finished_enable
|
||||||
|
#93 1 r 0 alarm_interrupt_enable
|
||||||
|
#94 1 r 0 periodic_interrupt_enable
|
||||||
|
#95 1 r 0 disable_clock_updates
|
||||||
|
#96 288 r 0 temporary_filler
|
||||||
|
0 384 r 0 reserved_memory
|
||||||
|
384 1 e 4 boot_option
|
||||||
|
385 1 e 4 last_boot
|
||||||
|
386 1 e 1 ECC_memory
|
||||||
|
388 4 r 0 reboot_bits
|
||||||
|
392 3 e 5 baud_rate
|
||||||
|
400 1 e 1 power_on_after_fail
|
||||||
|
412 4 e 6 debug_level
|
||||||
|
416 4 e 7 boot_first
|
||||||
|
420 4 e 7 boot_second
|
||||||
|
424 4 e 7 boot_third
|
||||||
|
428 4 h 0 boot_index
|
||||||
|
432 8 h 0 boot_countdown
|
||||||
|
1008 16 h 0 check_sum
|
||||||
|
|
||||||
|
enumerations
|
||||||
|
|
||||||
|
#ID value text
|
||||||
|
1 0 Disable
|
||||||
|
1 1 Enable
|
||||||
|
2 0 Enable
|
||||||
|
2 1 Disable
|
||||||
|
4 0 Fallback
|
||||||
|
4 1 Normal
|
||||||
|
5 0 115200
|
||||||
|
5 1 57600
|
||||||
|
5 2 38400
|
||||||
|
5 3 19200
|
||||||
|
5 4 9600
|
||||||
|
5 5 4800
|
||||||
|
5 6 2400
|
||||||
|
5 7 1200
|
||||||
|
6 6 Notice
|
||||||
|
6 7 Info
|
||||||
|
6 8 Debug
|
||||||
|
6 9 Spew
|
||||||
|
7 0 Network
|
||||||
|
7 1 HDD
|
||||||
|
7 2 Floppy
|
||||||
|
7 8 Fallback_Network
|
||||||
|
7 9 Fallback_HDD
|
||||||
|
7 10 Fallback_Floppy
|
||||||
|
#7 3 ROM
|
||||||
|
|
||||||
|
checksums
|
||||||
|
|
||||||
|
checksum 392 1007 1008
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,38 @@
|
||||||
|
#define ASSEMBLY 1
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include "arch/romcc_io.h"
|
||||||
|
#include "pc80/mc146818rtc_early.c"
|
||||||
|
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||||
|
#include "northbridge/amd/amdk8/early_ht.c"
|
||||||
|
#include "cpu/p6/boot_cpu.c"
|
||||||
|
#include "northbridge/amd/amdk8/reset_test.c"
|
||||||
|
|
||||||
|
static void main(void)
|
||||||
|
{
|
||||||
|
/* Nothing special needs to be done to find bus 0 */
|
||||||
|
/* Allow the HT devices to be found */
|
||||||
|
enumerate_ht_chain(0);
|
||||||
|
|
||||||
|
/* Setup the 8111 */
|
||||||
|
amd8111_enable_rom();
|
||||||
|
|
||||||
|
/* Is this a cpu reset? */
|
||||||
|
if (cpu_init_detected()) {
|
||||||
|
if (last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
} else {
|
||||||
|
asm("jmp __cpu_reset");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Is this a secondary cpu? */
|
||||||
|
else if (!boot_cpu() && last_boot_normal()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
/* This is the primary cpu how should I boot? */
|
||||||
|
else if (do_normal_boot()) {
|
||||||
|
asm("jmp __normal_image");
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,46 @@
|
||||||
|
/* This file was generated by getpir.c, do not modify!
|
||||||
|
(but if you do, please run checkpir on it to verify)
|
||||||
|
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||||
|
|
||||||
|
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/pirq_routing.h>
|
||||||
|
|
||||||
|
const struct irq_routing_table intel_irq_routing_table = {
|
||||||
|
PIRQ_SIGNATURE, /* u32 signature */
|
||||||
|
PIRQ_VERSION, /* u16 version */
|
||||||
|
32+16*22, /* there can be total 22 devices on the bus */
|
||||||
|
1, /* Where the interrupt router lies (bus) */
|
||||||
|
(4<<3)|3, /* Where the interrupt router lies (dev) */
|
||||||
|
0, /* IRQs devoted exclusively to PCI usage */
|
||||||
|
0x1022, /* Vendor */
|
||||||
|
0x7400, /* Device */
|
||||||
|
0, /* Crap (miniport) */
|
||||||
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
|
0x9a, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||||
|
{
|
||||||
|
{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{1,(3<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x4,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||||
|
{0x4,0x8, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x4,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||||
|
{0x4,0x18, {{0x2, 0xdef8}, {0x1, 0xdef8}, {0x3, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x4,0x28, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x4,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{1,(4<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{1,(1<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x2,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x2, 0},
|
||||||
|
{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x3, 0},
|
||||||
|
{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x2,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{1,(2<<3)|0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0x3,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
|
||||||
|
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
|
||||||
|
{0x3,0x20, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||||
|
{0x3,0x28, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
|
||||||
|
{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0,0xd0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
{0,0xd8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,192 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <device/chip.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <device/pci_ids.h>
|
||||||
|
#include <device/pci_ops.h>
|
||||||
|
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||||
|
#include "chip.h"
|
||||||
|
//#include <part/mainboard.h>
|
||||||
|
//#include "lsi_scsi.c"
|
||||||
|
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||||
|
{
|
||||||
|
0,1,2,3
|
||||||
|
};
|
||||||
|
#if 0
|
||||||
|
static void fixup_lsi_53c1030(struct device *pdev)
|
||||||
|
{
|
||||||
|
// uint8_t byte;
|
||||||
|
uint16_t word;
|
||||||
|
|
||||||
|
byte = 1;
|
||||||
|
pci_write_config8(pdev, 0xff, byte);
|
||||||
|
// Set the device id
|
||||||
|
// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
|
||||||
|
// Set the subsytem vendor id
|
||||||
|
// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);
|
||||||
|
word = 0x10f1;
|
||||||
|
pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
|
||||||
|
// Set the subsytem id
|
||||||
|
word = 0x4880;
|
||||||
|
pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
|
||||||
|
// Disable writes to the device id
|
||||||
|
byte = 0;
|
||||||
|
pci_write_config8(pdev, 0xff, byte);
|
||||||
|
|
||||||
|
// lsi_scsi_init(pdev);
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
//extern static void lsi_scsi_init(struct device *dev);
|
||||||
|
#if 0
|
||||||
|
static void print_pci_regs(struct device *dev)
|
||||||
|
{
|
||||||
|
uint8_t byte;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i=0;i<256;i++) {
|
||||||
|
byte = pci_read_config8(dev, i);
|
||||||
|
|
||||||
|
if((i%16)==0) printk_debug("\n%02x:",i);
|
||||||
|
printk_debug(" %02x",byte);
|
||||||
|
}
|
||||||
|
printk_debug("\n");
|
||||||
|
|
||||||
|
// pci_write_config8(dev, 0x4, byte);
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
static void print_mem(void)
|
||||||
|
{
|
||||||
|
int i;
|
||||||
|
int low_1MB = 0;
|
||||||
|
for(i=low_1MB;i<low_1MB+1024*4;i++) {
|
||||||
|
if((i%16)==0) printk_debug("\n %08x:",i);
|
||||||
|
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
|
||||||
|
}
|
||||||
|
|
||||||
|
for(i=low_1MB;i<low_1MB+1024*4;i++) {
|
||||||
|
if((i%16)==0) printk_debug("\n %08x:",i);
|
||||||
|
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
static void amd8111_enable_rom(void)
|
||||||
|
{
|
||||||
|
uint8_t byte;
|
||||||
|
struct device *dev;
|
||||||
|
|
||||||
|
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
|
||||||
|
/* Locate the amd8111 */
|
||||||
|
dev = dev_find_device(0x1022, 0x7468, 0);
|
||||||
|
|
||||||
|
/* Set the 4MB enable bit bit */
|
||||||
|
byte = pci_read_config8(dev, 0x43);
|
||||||
|
byte |= 0x80;
|
||||||
|
pci_write_config8(dev, 0x43, byte);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
static void onboard_scsi_fixup(void)
|
||||||
|
{
|
||||||
|
struct device *dev;
|
||||||
|
#if 0
|
||||||
|
unsigned char i,j,k;
|
||||||
|
|
||||||
|
for(i=0;i<=6;i++) {
|
||||||
|
for(j=0;j<=0x1f;j++) {
|
||||||
|
for (k=0;k<=6;k++){
|
||||||
|
dev = dev_find_slot(i, PCI_DEVFN(j, k));
|
||||||
|
if (dev) {
|
||||||
|
printk_debug("%02x:%02x:%02x",i,j,k);
|
||||||
|
print_pci_regs(dev);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
|
||||||
|
if(!dev) {
|
||||||
|
printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
lsi_scsi_init(dev);
|
||||||
|
#endif
|
||||||
|
// print_mem();
|
||||||
|
// amd8111_enable_rom();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#if 0
|
||||||
|
static void vga_fixup(void) {
|
||||||
|
// we do this right here because:
|
||||||
|
// - all the hardware is working, and some VGA bioses seem to need
|
||||||
|
// that
|
||||||
|
// - we need page 0 below for linuxbios tables.
|
||||||
|
#if CONFIG_REALMODE_IDT == 1
|
||||||
|
printk_debug("INSTALL REAL-MODE IDT\n");
|
||||||
|
setup_realmode_idt();
|
||||||
|
#endif
|
||||||
|
#if CONFIG_VGABIOS == 1
|
||||||
|
printk_debug("DO THE VGA BIOS\n");
|
||||||
|
do_vgabios();
|
||||||
|
post_code(0x93);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static void
|
||||||
|
enable(struct chip *chip, enum chip_pass pass)
|
||||||
|
{
|
||||||
|
|
||||||
|
struct mainboard_tyan_s4880_config *conf =
|
||||||
|
(struct mainboard_tyan_s4880_config *)chip->chip_info;
|
||||||
|
|
||||||
|
switch (pass) {
|
||||||
|
default: break;
|
||||||
|
// case CONF_PASS_PRE_CONSOLE:
|
||||||
|
// case CONF_PASS_PRE_PCI:
|
||||||
|
// case CONF_PASS_POST_PCI:
|
||||||
|
case CONF_PASS_PRE_BOOT:
|
||||||
|
// if (conf->fixup_scsi)
|
||||||
|
// onboard_scsi_fixup();
|
||||||
|
// if (conf->fixup_vga)
|
||||||
|
// vga_fixup();
|
||||||
|
printk_debug("mainboard fixup pass %d done\r\n",
|
||||||
|
pass);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
static struct device_operations mainboard_operations = {
|
||||||
|
.read_resources = root_dev_read_resources,
|
||||||
|
.set_resources = root_dev_set_resources,
|
||||||
|
.enable_resources = enable_childrens_resources,
|
||||||
|
.init = 0,
|
||||||
|
.scan_bus = amdk8_scan_root_bus,
|
||||||
|
.enable = 0,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void enumerate(struct chip *chip)
|
||||||
|
{
|
||||||
|
struct chip *child;
|
||||||
|
dev_root.ops = &mainboard_operations;
|
||||||
|
chip->dev = &dev_root;
|
||||||
|
chip->bus = 0;
|
||||||
|
for(child = chip->children; child; child = child->next) {
|
||||||
|
child->bus = &dev_root.link[0];
|
||||||
|
}
|
||||||
|
}
|
||||||
|
struct chip_control mainboard_tyan_s4880_control = {
|
||||||
|
.enable = enable,
|
||||||
|
.enumerate = enumerate,
|
||||||
|
.name = "Tyan s4880 mainboard ",
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,198 @@
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <arch/smp/mpspec.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||||
|
{
|
||||||
|
static const char sig[4] = "PCMP";
|
||||||
|
static const char oem[8] = "TYAN ";
|
||||||
|
static const char productid[12] = "S4880 ";
|
||||||
|
struct mp_config_table *mc;
|
||||||
|
|
||||||
|
unsigned char bus_num;
|
||||||
|
unsigned char bus_isa;
|
||||||
|
unsigned char bus_8131_1;
|
||||||
|
unsigned char bus_8131_2;
|
||||||
|
unsigned char bus_8111_1;
|
||||||
|
|
||||||
|
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||||
|
memset(mc, 0, sizeof(*mc));
|
||||||
|
|
||||||
|
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||||
|
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||||
|
mc->mpc_spec = 0x04;
|
||||||
|
mc->mpc_checksum = 0; /* not yet computed */
|
||||||
|
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||||
|
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||||
|
mc->mpc_oemptr = 0;
|
||||||
|
mc->mpc_oemsize = 0;
|
||||||
|
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||||
|
mc->mpc_lapic = LAPIC_ADDR;
|
||||||
|
mc->mpe_length = 0;
|
||||||
|
mc->mpe_checksum = 0;
|
||||||
|
mc->reserved = 0;
|
||||||
|
|
||||||
|
smp_write_processors(mc, processor_map);
|
||||||
|
|
||||||
|
|
||||||
|
{
|
||||||
|
device_t dev;
|
||||||
|
|
||||||
|
/* 8111 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||||
|
bus_isa++;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8111_1 = 4;
|
||||||
|
bus_isa = 5;
|
||||||
|
}
|
||||||
|
/* 8131-1 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_1 = 2;
|
||||||
|
}
|
||||||
|
/* 8131-2 */
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||||
|
if (dev) {
|
||||||
|
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||||
|
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||||
|
|
||||||
|
bus_8131_2 = 3;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*Bus: Bus ID Type*/
|
||||||
|
/* define bus and isa numbers */
|
||||||
|
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||||
|
smp_write_bus(mc, bus_num, "PCI ");
|
||||||
|
}
|
||||||
|
smp_write_bus(mc, bus_isa, "ISA ");
|
||||||
|
|
||||||
|
|
||||||
|
/*I/O APICs: APIC ID Version State Address*/
|
||||||
|
smp_write_ioapic(mc, 4, 0x11, 0xfec00000);
|
||||||
|
{
|
||||||
|
struct pci_dev *dev;
|
||||||
|
uint32_t base;
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
|
||||||
|
if (dev) {
|
||||||
|
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||||
|
smp_write_ioapic(mc, 5, 0x11, base);
|
||||||
|
}
|
||||||
|
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
|
||||||
|
if (dev) {
|
||||||
|
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||||
|
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||||
|
smp_write_ioapic(mc, 6, 0x11, base);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||||
|
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x4, 0x0);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x4, 0x1);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x4, 0x2);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x4, 0x3);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x4, 0x4);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x5, 0x4, 0x5);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x4, 0x6);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x4, 0x7);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x4, 0x8);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x9, 0x4, 0x9);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xa, 0x4, 0xa);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xb, 0x4, 0xb);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x4, 0xc);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x4, 0xd);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x4, 0xe);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x4, 0xf);
|
||||||
|
|
||||||
|
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, 0x4, 0x13);
|
||||||
|
|
||||||
|
|
||||||
|
//On Board AMD USB
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x4, 0x13);
|
||||||
|
|
||||||
|
//On Board Via USB 1.1 and 2
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|0, 0x4, 0x11); //1.1
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|1, 0x4, 0x12); //1.1
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (3<<2)|2, 0x4, 0x10); //2
|
||||||
|
|
||||||
|
//Slot 5 PCI 32
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x4, 0x10);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, 0x4, 0x11);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, 0x4, 0x12); //
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, 0x4, 0x13); //
|
||||||
|
|
||||||
|
|
||||||
|
//On Board SI Serial ATA
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x4, 0x13);
|
||||||
|
//On Board ATI Display Adapter
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x4, 0x12);
|
||||||
|
|
||||||
|
|
||||||
|
//Slot 4 PCIX 100/66
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, 0x5, 0x3);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, 0x5, 0x0);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, 0x5, 0x1);//
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, 0x5, 0x2);//
|
||||||
|
|
||||||
|
//Slot 3 PCIX 100/66
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, 0x5, 0x2);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, 0x5, 0x3);//
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, 0x5, 0x0);//
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, 0x5, 0x1);//
|
||||||
|
|
||||||
|
//On Board LSI scsi and NIC
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, 0x5, 0x0);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, 0x5, 0x1);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x5, 0x0);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x5, 0x1);
|
||||||
|
|
||||||
|
//Slot 2 PCI-X 133/100/66
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x6, 0x0);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x6, 0x1);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x6, 0x2); //
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x6, 0x3); //
|
||||||
|
|
||||||
|
//Slot 1 PCI-X 133/100/66
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, 0x6, 0x1);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, 0x6, 0x2);
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, 0x6, 0x3);//
|
||||||
|
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, 0x6, 0x0);//
|
||||||
|
|
||||||
|
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||||
|
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||||
|
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||||
|
/* There is no extension information... */
|
||||||
|
|
||||||
|
/* Compute the checksums */
|
||||||
|
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||||
|
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||||
|
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||||
|
mc, smp_next_mpe_entry(mc));
|
||||||
|
return smp_next_mpe_entry(mc);
|
||||||
|
}
|
||||||
|
|
||||||
|
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||||
|
{
|
||||||
|
void *v;
|
||||||
|
v = smp_write_floating_table(addr);
|
||||||
|
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,264 @@
|
||||||
|
/*
|
||||||
|
* Tyan S4880 needs a different resource map
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
static void setup_s4880_resource_map(void)
|
||||||
|
{
|
||||||
|
static const unsigned int register_values[] = {
|
||||||
|
/* Careful set limit registers before base registers which contain the enables */
|
||||||
|
/* DRAM Limit i Registers
|
||||||
|
* F1:0x44 i = 0
|
||||||
|
* F1:0x4C i = 1
|
||||||
|
* F1:0x54 i = 2
|
||||||
|
* F1:0x5C i = 3
|
||||||
|
* F1:0x64 i = 4
|
||||||
|
* F1:0x6C i = 5
|
||||||
|
* F1:0x74 i = 6
|
||||||
|
* F1:0x7C i = 7
|
||||||
|
* [ 2: 0] Destination Node ID
|
||||||
|
* 000 = Node 0
|
||||||
|
* 001 = Node 1
|
||||||
|
* 010 = Node 2
|
||||||
|
* 011 = Node 3
|
||||||
|
* 100 = Node 4
|
||||||
|
* 101 = Node 5
|
||||||
|
* 110 = Node 6
|
||||||
|
* 111 = Node 7
|
||||||
|
* [ 7: 3] Reserved
|
||||||
|
* [10: 8] Interleave select
|
||||||
|
* specifies the values of A[14:12] to use with interleave enable.
|
||||||
|
* [15:11] Reserved
|
||||||
|
* [31:16] DRAM Limit Address i Bits 39-24
|
||||||
|
* This field defines the upper address bits of a 40 bit address
|
||||||
|
* that define the end of the DRAM region.
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
|
||||||
|
/* DRAM Base i Registers
|
||||||
|
* F1:0x40 i = 0
|
||||||
|
* F1:0x48 i = 1
|
||||||
|
* F1:0x50 i = 2
|
||||||
|
* F1:0x58 i = 3
|
||||||
|
* F1:0x60 i = 4
|
||||||
|
* F1:0x68 i = 5
|
||||||
|
* F1:0x70 i = 6
|
||||||
|
* F1:0x78 i = 7
|
||||||
|
* [ 0: 0] Read Enable
|
||||||
|
* 0 = Reads Disabled
|
||||||
|
* 1 = Reads Enabled
|
||||||
|
* [ 1: 1] Write Enable
|
||||||
|
* 0 = Writes Disabled
|
||||||
|
* 1 = Writes Enabled
|
||||||
|
* [ 7: 2] Reserved
|
||||||
|
* [10: 8] Interleave Enable
|
||||||
|
* 000 = No interleave
|
||||||
|
* 001 = Interleave on A[12] (2 nodes)
|
||||||
|
* 010 = reserved
|
||||||
|
* 011 = Interleave on A[12] and A[14] (4 nodes)
|
||||||
|
* 100 = reserved
|
||||||
|
* 101 = reserved
|
||||||
|
* 110 = reserved
|
||||||
|
* 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
|
||||||
|
* [15:11] Reserved
|
||||||
|
* [13:16] DRAM Base Address i Bits 39-24
|
||||||
|
* This field defines the upper address bits of a 40-bit address
|
||||||
|
* that define the start of the DRAM region.
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
|
||||||
|
|
||||||
|
/* Memory-Mapped I/O Limit i Registers
|
||||||
|
* F1:0x84 i = 0
|
||||||
|
* F1:0x8C i = 1
|
||||||
|
* F1:0x94 i = 2
|
||||||
|
* F1:0x9C i = 3
|
||||||
|
* F1:0xA4 i = 4
|
||||||
|
* F1:0xAC i = 5
|
||||||
|
* F1:0xB4 i = 6
|
||||||
|
* F1:0xBC i = 7
|
||||||
|
* [ 2: 0] Destination Node ID
|
||||||
|
* 000 = Node 0
|
||||||
|
* 001 = Node 1
|
||||||
|
* 010 = Node 2
|
||||||
|
* 011 = Node 3
|
||||||
|
* 100 = Node 4
|
||||||
|
* 101 = Node 5
|
||||||
|
* 110 = Node 6
|
||||||
|
* 111 = Node 7
|
||||||
|
* [ 3: 3] Reserved
|
||||||
|
* [ 5: 4] Destination Link ID
|
||||||
|
* 00 = Link 0
|
||||||
|
* 01 = Link 1
|
||||||
|
* 10 = Link 2
|
||||||
|
* 11 = Reserved
|
||||||
|
* [ 6: 6] Reserved
|
||||||
|
* [ 7: 7] Non-Posted
|
||||||
|
* 0 = CPU writes may be posted
|
||||||
|
* 1 = CPU writes must be non-posted
|
||||||
|
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
|
||||||
|
* This field defines the upp adddress bits of a 40-bit address that
|
||||||
|
* defines the end of a memory-mapped I/O region n
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
|
||||||
|
|
||||||
|
/* Memory-Mapped I/O Base i Registers
|
||||||
|
* F1:0x80 i = 0
|
||||||
|
* F1:0x88 i = 1
|
||||||
|
* F1:0x90 i = 2
|
||||||
|
* F1:0x98 i = 3
|
||||||
|
* F1:0xA0 i = 4
|
||||||
|
* F1:0xA8 i = 5
|
||||||
|
* F1:0xB0 i = 6
|
||||||
|
* F1:0xB8 i = 7
|
||||||
|
* [ 0: 0] Read Enable
|
||||||
|
* 0 = Reads disabled
|
||||||
|
* 1 = Reads Enabled
|
||||||
|
* [ 1: 1] Write Enable
|
||||||
|
* 0 = Writes disabled
|
||||||
|
* 1 = Writes Enabled
|
||||||
|
* [ 2: 2] Cpu Disable
|
||||||
|
* 0 = Cpu can use this I/O range
|
||||||
|
* 1 = Cpu requests do not use this I/O range
|
||||||
|
* [ 3: 3] Lock
|
||||||
|
* 0 = base/limit registers i are read/write
|
||||||
|
* 1 = base/limit registers i are read-only
|
||||||
|
* [ 7: 4] Reserved
|
||||||
|
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
|
||||||
|
* This field defines the upper address bits of a 40bit address
|
||||||
|
* that defines the start of memory-mapped I/O region i
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
|
||||||
|
|
||||||
|
/* PCI I/O Limit i Registers
|
||||||
|
* F1:0xC4 i = 0
|
||||||
|
* F1:0xCC i = 1
|
||||||
|
* F1:0xD4 i = 2
|
||||||
|
* F1:0xDC i = 3
|
||||||
|
* [ 2: 0] Destination Node ID
|
||||||
|
* 000 = Node 0
|
||||||
|
* 001 = Node 1
|
||||||
|
* 010 = Node 2
|
||||||
|
* 011 = Node 3
|
||||||
|
* 100 = Node 4
|
||||||
|
* 101 = Node 5
|
||||||
|
* 110 = Node 6
|
||||||
|
* 111 = Node 7
|
||||||
|
* [ 3: 3] Reserved
|
||||||
|
* [ 5: 4] Destination Link ID
|
||||||
|
* 00 = Link 0
|
||||||
|
* 01 = Link 1
|
||||||
|
* 10 = Link 2
|
||||||
|
* 11 = reserved
|
||||||
|
* [11: 6] Reserved
|
||||||
|
* [24:12] PCI I/O Limit Address i
|
||||||
|
* This field defines the end of PCI I/O region n
|
||||||
|
* [31:25] Reserved
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
|
||||||
|
|
||||||
|
/* PCI I/O Base i Registers
|
||||||
|
* F1:0xC0 i = 0
|
||||||
|
* F1:0xC8 i = 1
|
||||||
|
* F1:0xD0 i = 2
|
||||||
|
* F1:0xD8 i = 3
|
||||||
|
* [ 0: 0] Read Enable
|
||||||
|
* 0 = Reads Disabled
|
||||||
|
* 1 = Reads Enabled
|
||||||
|
* [ 1: 1] Write Enable
|
||||||
|
* 0 = Writes Disabled
|
||||||
|
* 1 = Writes Enabled
|
||||||
|
* [ 3: 2] Reserved
|
||||||
|
* [ 4: 4] VGA Enable
|
||||||
|
* 0 = VGA matches Disabled
|
||||||
|
* 1 = matches all address < 64K and where A[9:0] is in the
|
||||||
|
* range 3B0-3BB or 3C0-3DF independen of the base & limit registers
|
||||||
|
* [ 5: 5] ISA Enable
|
||||||
|
* 0 = ISA matches Disabled
|
||||||
|
* 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
|
||||||
|
* from matching agains this base/limit pair
|
||||||
|
* [11: 6] Reserved
|
||||||
|
* [24:12] PCI I/O Base i
|
||||||
|
* This field defines the start of PCI I/O region n
|
||||||
|
* [31:25] Reserved
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
|
||||||
|
|
||||||
|
/* Config Base and Limit i Registers
|
||||||
|
* F1:0xE0 i = 0
|
||||||
|
* F1:0xE4 i = 1
|
||||||
|
* F1:0xE8 i = 2
|
||||||
|
* F1:0xEC i = 3
|
||||||
|
* [ 0: 0] Read Enable
|
||||||
|
* 0 = Reads Disabled
|
||||||
|
* 1 = Reads Enabled
|
||||||
|
* [ 1: 1] Write Enable
|
||||||
|
* 0 = Writes Disabled
|
||||||
|
* 1 = Writes Enabled
|
||||||
|
* [ 2: 2] Device Number Compare Enable
|
||||||
|
* 0 = The ranges are based on bus number
|
||||||
|
* 1 = The ranges are ranges of devices on bus 0
|
||||||
|
* [ 3: 3] Reserved
|
||||||
|
* [ 6: 4] Destination Node
|
||||||
|
* 000 = Node 0
|
||||||
|
* 001 = Node 1
|
||||||
|
* 010 = Node 2
|
||||||
|
* 011 = Node 3
|
||||||
|
* 100 = Node 4
|
||||||
|
* 101 = Node 5
|
||||||
|
* 110 = Node 6
|
||||||
|
* 111 = Node 7
|
||||||
|
* [ 7: 7] Reserved
|
||||||
|
* [ 9: 8] Destination Link
|
||||||
|
* 00 = Link 0
|
||||||
|
* 01 = Link 1
|
||||||
|
* 10 = Link 2
|
||||||
|
* 11 - Reserved
|
||||||
|
* [15:10] Reserved
|
||||||
|
* [23:16] Bus Number Base i
|
||||||
|
* This field defines the lowest bus number in configuration region i
|
||||||
|
* [31:24] Bus Number Limit i
|
||||||
|
* This field defines the highest bus number in configuration regin i
|
||||||
|
*/
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000203,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
|
||||||
|
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
|
||||||
|
};
|
||||||
|
int max;
|
||||||
|
max = sizeof(register_values)/sizeof(register_values[0]);
|
||||||
|
setup_resource_map(register_values, max);
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Reference in New Issue