amd/agesa/family14,15 & 16: Remove unnecessary whitespace

Change-Id: I9495b47a85a6fb9d8d06d9a82c0444b794ec4933
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/cpu/amd/agesa/family14/model_14_init.c

@@ -42,7 +42,7 @@ static void model_14_init(device_t dev)
 #endif
 	printk(BIOS_DEBUG, "Model 14 Init.\n");
 
-	disable_cache ();
+	disable_cache();
 	/*
 	 * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set
 	 * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14.

src/cpu/amd/agesa/family15tn/model_15_init.c

@@ -46,7 +46,7 @@ static void model_15_init(device_t dev)
 	//x86_enable_cache();
 	//amd_setup_mtrrs();
 	//x86_mtrr_check();
-	disable_cache ();
+	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;

src/cpu/amd/agesa/family16kb/model_16_init.c

@@ -44,7 +44,7 @@ static void model_16_init(device_t dev)
 	//x86_enable_cache();
 	//amd_setup_mtrrs();
 	//x86_mtrr_check();
-	disable_cache ();
+	disable_cache();
 	/* Enable access to AMD RdDram and WrDram extension bits */
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;