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intel/i945 gm45: Use acpi_s3_resume_allowed() 

Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6061
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Kyösti Mälkki 2014-06-14 18:51:34 +03:00
parent 2ca2afe760
commit 12d681b23f
8 changed files with 88 additions and 85 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/mainboard/getac/p470/romstage.c
View File

@ -26,6 +26,7 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
@ -304,17 +305,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
} else {
#else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); }
#endif
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

21
src/mainboard/ibase/mb899/romstage.c
View File

@ -26,6 +26,7 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <superio/winbond/common/winbond.h> #include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627ehg/w83627ehg.h> #include <superio/winbond/w83627ehg/w83627ehg.h>
@ -255,16 +256,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
#else } else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif }
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

21
src/mainboard/intel/d945gclf/romstage.c
View File

@ -26,6 +26,7 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include "superio/smsc/lpc47m15x/lpc47m15x.h" #include "superio/smsc/lpc47m15x/lpc47m15x.h"
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
@ -215,16 +216,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
#else } else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif }
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

22
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -22,6 +22,7 @@
#include <stdint.h> #include <stdint.h>
#include <string.h> #include <string.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <arch/io.h> #include <arch/io.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -366,17 +367,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
} else {
#else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); }
#endif
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

22
src/mainboard/lenovo/t60/romstage.c
View File

@ -29,6 +29,7 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <timestamp.h> #include <timestamp.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
@ -264,17 +265,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
} else {
#else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); }
#endif
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

22
src/mainboard/lenovo/x60/romstage.c
View File

@ -29,6 +29,7 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <timestamp.h> #include <timestamp.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
@ -266,17 +267,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
} else {
#else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); }
#endif
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

22
src/mainboard/roda/rk886ex/romstage.c
View File

@ -28,6 +28,7 @@
#include <device/pnp_def.h> #include <device/pnp_def.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <lib.h> #include <lib.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
#include <console/console.h> #include <console/console.h>
@ -291,17 +292,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04); reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) { if (((reg32 >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
boot_mode = 2; boot_mode = 2;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
} else {
#else printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); }
#endif
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

21
src/mainboard/roda/rk9/romstage.c
View File

@ -27,6 +27,7 @@
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include <arch/acpi.h>
#include <cbmem.h> #include <cbmem.h>
#include <lib.h> #include <lib.h>
#include <pc80/mc146818rtc.h> #include <pc80/mc146818rtc.h>
@ -155,16 +156,16 @@ void main(unsigned long bist)
/* Check for S3 resume. */ /* Check for S3 resume. */
const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04);
if (((pm1_cnt >> 10) & 7) == 5) { if (((pm1_cnt >> 10) & 7) == 5) {
#if CONFIG_HAVE_ACPI_RESUME if (acpi_s3_resume_allowed()) {
printk(BIOS_DEBUG, "Resume from S3 detected.\n"); printk(BIOS_DEBUG, "Resume from S3 detected.\n");
s3resume = 1; s3resume = 1;
/* Clear SLP_TYPE. This will break stage2 but /* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there. * we care for that when we get there.
*/ */
outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04);
#else } else {
printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
#endif }
} }
/* RAM initialization */ /* RAM initialization */