arm: Import armv7_dcache_wbinv_all function from NetBSD
This patch pulls in NetBSD's full cache flushing algorithm for ARM, to replace our old, slow and slightly overzealous C-only implementation. It's a beautiful piece of code that manages to run on only caller-saved registers (meaning it doesn't need to write to memory) in a very tight loop, and it's BSD-licensed to boot (which we need for libpayload). Unfortunately it's also not quite correct, but I can fix that. Pulling the original in a separate commit to make it more obvious what changes are mine. Change-Id: I7a71c9e570866a6e25f756cb09ae2b6445048d83 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183878 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4698467320613d7ddc39714f40aacbc990af9399) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6931 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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/*
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* Optimized assembly for low-level CPU operations on ARMv7 processors.
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*
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* Cache flushing code based off sys/arch/arm/arm/cpufunc_asm_armv7.S in NetBSD
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*
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* Copyright (c) 2010 Per Odlund <per.odlund@armagedon.se>
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* Copyright (c) 2014 Google Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* These work very hard to not push registers onto the stack and to limit themselves
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* to use r0-r3 and ip.
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*/
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/* * LINTSTUB: void armv7_dcache_wbinv_all(void); */
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ENTRY_NP(armv7_dcache_wbinv_all)
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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ands r3, r0, #0x07000000
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beq .Ldone_wbinv
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lsr r3, r3, #23 @ left align loc (low 4 bits)
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mov r1, #0
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.Lstart_wbinv:
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add r2, r3, r3, lsr #1 @ r2 = level * 3 / 2
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mov r1, r0, lsr r2 @ r1 = cache type
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bfc r1, #3, #28
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cmp r1, #2 @ is it data or i&d?
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blt .Lnext_level_wbinv @ nope, skip level
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mcr p15, 2, r3, c0, c0, 0 @ select cache level
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isb
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mrc p15, 1, r0, c0, c0, 0 @ read CCSIDR
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ubfx ip, r0, #0, #3 @ get linesize from CCSIDR
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add ip, ip, #4 @ apply bias
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ubfx r2, r0, #13, #15 @ get numsets - 1 from CCSIDR
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lsl r2, r2, ip @ shift to set position
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orr r3, r3, r2 @ merge set into way/set/level
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mov r1, #1
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lsl r1, r1, ip @ r1 = set decr
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ubfx ip, r0, #3, #10 @ get numways - 1 from [to be discarded] CCSIDR
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clz r2, ip @ number of bits to MSB of way
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lsl ip, ip, r2 @ shift by that into way position
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mov r0, #1 @
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lsl r2, r0, r2 @ r2 now contains the way decr
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mov r0, r3 @ get sets/level (no way yet)
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orr r3, r3, ip @ merge way into way/set/level
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bfc r0, #0, #4 @ clear low 4 bits (level) to get numset - 1
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sub r2, r2, r0 @ subtract from way decr
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/* r3 = ways/sets/level, r2 = way decr, r1 = set decr, r0 and ip are free */
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1: mcr p15, 0, r3, c7, c14, 2 @ writeback and invalidate line
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cmp r3, #15 @ are we done with this level (way/set == 0)
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bls .Lnext_level_wbinv @ yes, go to next level
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lsl r0, r3, #10 @ clear way bits leaving only set/level bits
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lsr r0, r0, #4 @ clear level bits leaving only set bits
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subne r3, r3, r1 @ non-zero?, decrement set #
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subeq r3, r3, r2 @ zero?, decrement way # and restore set count
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b 1b
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.Lnext_level_wbinv:
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mrc p15, 1, r0, c0, c0, 1 @ read CLIDR
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and ip, r0, #0x07000000 @ narrow to LoC
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lsr ip, ip, #23 @ left align LoC (low 4 bits)
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add r3, r3, #2 @ go to next level
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cmp r3, ip @ compare
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blt .Lstart_wbinv @ not done, next level (r0 == CLIDR)
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.Ldone_wbinv:
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mov r0, #0 @ default back to cache level 0
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mcr p15, 2, r0, c0, c0, 0 @ select cache level
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dsb
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isb
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bx lr
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END(armv7_dcache_wbinv_all)
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