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superio/ite: Improve code formatting 

Change-Id: I014659aaddeb9fa2d5c3c3583e9379be4f9db69b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39929
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-03-30 16:45:35 +02:00 committed by Felix Held
parent 7774de53d4
commit 12eef084fd
6 changed files with 13 additions and 16 deletions
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12
src/superio/ite/common/early_serial.c
View File

@ -8,12 +8,12 @@
#include "ite.h"
/* Global configuration registers. */
#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */
#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */
#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
#define ITE_CONFIG_REG_MFC 0x2a /* multi function pin */
#define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */
/* Helper procedure */
static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value)

6
src/superio/ite/common/env_ctrl.c
View File

@ -81,8 +81,7 @@ static void enable_tmpin(const u16 base, const u8 tmpin,
reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin);
break;
default:
printk(BIOS_WARNING,
"Unsupported thermal mode 0x%x on TMPIN%d\n",
printk(BIOS_WARNING, "Unsupported thermal mode 0x%x on TMPIN%d\n",
conf->mode, tmpin);
return;
}
@ -185,8 +184,7 @@ static void enable_fan(const u16 base, const u8 fan,
pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg);
}
if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG)
&& conf->mode >= FAN_MODE_ON) {
if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) {
reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE);
reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan);
pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg);

2
src/superio/ite/it8720f/acpi/superio.asl
View File

@ -50,7 +50,7 @@ Device(SUPERIO_DEV) {
Field (CREG, ByteAcc, NoLock, Preserve)
{
PNP_ADDR_REG, 8,
PNP_DATA_REG, 8
PNP_DATA_REG, 8
}
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{

2
src/superio/ite/it8721f/acpi/superio.asl
View File

@ -50,7 +50,7 @@ Device(SUPERIO_DEV) {
Field (CREG, ByteAcc, NoLock, Preserve)
{
PNP_ADDR_REG, 8,
PNP_DATA_REG, 8
PNP_DATA_REG, 8
}
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{

2
src/superio/ite/it8783ef/acpi/superio.asl
View File

@ -56,7 +56,7 @@ Device(SUPERIO_DEV) {
Field (CREG, ByteAcc, NoLock, Preserve)
{
PNP_ADDR_REG, 8,
PNP_DATA_REG, 8
PNP_DATA_REG, 8
}
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{

5
src/superio/ite/it8786e/acpi/superio.asl
View File

@ -55,7 +55,7 @@ Device (SUPERIO_DEV) {
Field (CREG, ByteAcc, NoLock, Preserve)
{
PNP_ADDR_REG, 8,
PNP_DATA_REG, 8
PNP_DATA_REG, 8
}
IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve)
{
@ -83,8 +83,7 @@ Device (SUPERIO_DEV) {
{
/* Announce the used i/o ports to the OS */
Return (ResourceTemplate () {
IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE,
0x01, 0x02)
IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
})
}