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superio/ite: Improve code formatting 

Change-Id: I014659aaddeb9fa2d5c3c3583e9379be4f9db69b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39929
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-03-30 16:45:35 +02:00 committed by Felix Held
parent 7774de53d4
commit 12eef084fd
6 changed files with 13 additions and 16 deletions
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6
src/superio/ite/common/env_ctrl.c
View File

@ -81,8 +81,7 @@ static void enable_tmpin(const u16 base, const u8 tmpin,
reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin); reg |= ITE_EC_ADC_TEMP_RESISTOR_MODE(tmpin);
break; break;
default: default:
printk(BIOS_WARNING, printk(BIOS_WARNING, "Unsupported thermal mode 0x%x on TMPIN%d\n",
"Unsupported thermal mode 0x%x on TMPIN%d\n",
conf->mode, tmpin); conf->mode, tmpin);
return; return;
} }
@ -185,8 +184,7 @@ static void enable_fan(const u16 base, const u8 fan,
pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg); pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_MODE, reg);
} }
if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) if (CONFIG(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) {
&& conf->mode >= FAN_MODE_ON) {
reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg = pnp_read_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE);
reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan);
pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg); pnp_write_hwm5_index(base, ITE_EC_FAN_TAC_COUNTER_ENABLE, reg);

3
src/superio/ite/it8786e/acpi/superio.asl
View File

@ -83,8 +83,7 @@ Device (SUPERIO_DEV) {
{ {
/* Announce the used i/o ports to the OS */ /* Announce the used i/o ports to the OS */
Return (ResourceTemplate () { Return (ResourceTemplate () {
IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
0x01, 0x02)
}) })
} }