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soc/intel/alderlake: enable gpio locking 

This change supplies a list of ADL gpios that are connected to non-host
(x86) controllers and should be locked after initial configuration.

Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking.

BUG=b:210430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.

Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Nick Vaccaro 2021-10-12 18:53:16 -07:00
parent b6f29c9bf4
commit 12f216bf87
2 changed files with 58 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/alderlake/Kconfig
View File

@ -82,6 +82,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS
select SOC_INTEL_COMMON_BLOCK_TCSS select SOC_INTEL_COMMON_BLOCK_TCSS
select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC
select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4

57
src/soc/intel/alderlake/gpio.c
View File

@ -247,3 +247,60 @@ const struct pmc_to_gpio_route *soc_pmc_gpio_routes(size_t *num)
*num = ARRAY_SIZE(routes); *num = ARRAY_SIZE(routes);
return routes; return routes;
}; };
/* GPIOs controllable by non-host (x86) agent, eg. ISH, THC, etc */
static const struct gpio_lock_config gpios_to_lock[] = {
{ GPP_A16, GPIO_LOCK_CONFIG }, /* ISH_GP5 NF4 */
{ GPP_B3, GPIO_LOCK_CONFIG }, /* ISH_GP4B NF4 (not avail in ADL PCH-M) */
{ GPP_B4, GPIO_LOCK_CONFIG }, /* ISH_GP5B NF4 (not avail in ADL PCH-M) */
{ GPP_B5, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SDA NF1 */
{ GPP_B6, GPIO_LOCK_CONFIG }, /* ISH_I2C0_SCL NF1 */
{ GPP_B7, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SDA NF1 */
{ GPP_B8, GPIO_LOCK_CONFIG }, /* ISH_I2C1_SCL NF1 */
{ GPP_B14, GPIO_LOCK_CONFIG }, /* ISH_GP6 NF5 */
{ GPP_B15, GPIO_LOCK_CONFIG }, /* ISH_GP7 NF5 */
{ GPP_B16, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SDA NF4 */
{ GPP_B17, GPIO_LOCK_CONFIG }, /* ISH_I2C2_SCL NF4 */
{ GPP_D0, GPIO_LOCK_CONFIG }, /* ISH_GP0 NF1 */
{ GPP_D1, GPIO_LOCK_CONFIG }, /* ISH_GP1 NF1 */
{ GPP_D2, GPIO_LOCK_CONFIG }, /* ISH_GP2 NF1 */
{ GPP_D3, GPIO_LOCK_CONFIG }, /* ISH_GP3 NF1 */
{ GPP_D9, GPIO_LOCK_CONFIG }, /* ISH_SPI_CS# NF1 */
{ GPP_D10, GPIO_LOCK_CONFIG }, /* ISH_SPI_CLK NF1 */
{ GPP_D11, GPIO_LOCK_CONFIG }, /* ISH_SPI_MISO NF1 */
{ GPP_D12, GPIO_LOCK_CONFIG }, /* ISH_SPI_MOSI NF1 */
{ GPP_D13, GPIO_LOCK_CONFIG }, /* ISH_UART0_RXD NF1 */
{ GPP_D14, GPIO_LOCK_CONFIG }, /* ISH_UART0_TXD NF1 */
{ GPP_D15, GPIO_LOCK_CONFIG }, /* ISH_UART0_RTS# NF1 */
{ GPP_D16, GPIO_LOCK_CONFIG }, /* ISH_UART0_CTS# NF1 */
{ GPP_D17, GPIO_LOCK_CONFIG }, /* ISH_UART1_RXD NF2 */
{ GPP_D18, GPIO_LOCK_CONFIG }, /* ISH_UART1_TXD NF2 */
{ GPP_E9, GPIO_LOCK_CONFIG }, /* ISH_GP4 NF2 */
{ GPP_H12, GPIO_LOCK_CONFIG }, /* ISH_GP6B NF4 */
{ GPP_H13, GPIO_LOCK_CONFIG }, /* ISH_GP7B NF4 */
{ GPP_E1, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO2 NF2 */
{ GPP_E2, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO3 NF2 */
{ GPP_E6, GPIO_LOCK_CONFIG }, /* THC0_SPI1_RST# NF2 */
{ GPP_E10, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CS# NF2 */
{ GPP_E11, GPIO_LOCK_CONFIG }, /* THC0_SPI1_CLK NF2 */
{ GPP_E12, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO1 NF2 */
{ GPP_E13, GPIO_LOCK_CONFIG }, /* THC0_SPI1_IO0 NF2 */
{ GPP_E17, GPIO_LOCK_CONFIG }, /* THC0_SPI1_INT# NF2 */
{ GPP_F11, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CLK NF3 */
{ GPP_F12, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO0 NF3 */
{ GPP_F13, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO1 NF3 */
{ GPP_F14, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO2 NF3 */
{ GPP_F15, GPIO_LOCK_CONFIG }, /* THC1_SPI2_IO3 NF3 */
{ GPP_F16, GPIO_LOCK_CONFIG }, /* THC1_SPI2_CS# NF3 */
{ GPP_F17, GPIO_LOCK_CONFIG }, /* THC1_SPI2_RST# NF3 */
{ GPP_F18, GPIO_LOCK_CONFIG }, /* THC1_SPI2_INT# NF3 */
{ GPP_H3, GPIO_LOCK_CONFIG }, /* SX_EXIT_HOLDOFF# NF1 */
};
const struct gpio_lock_config *soc_gpio_lock_config(size_t *num)
{
*num = ARRAY_SIZE(gpios_to_lock);
return gpios_to_lock;
}