src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: Remove unused headers
Header files AcpiLib.h, FchDef.h and FchBiosRamUsage.h became obsolete when VENDORCODE_FULL_SUPPORT was removed. Therefor they should be removed. BUG=b:112602580 TEST=Build grunt and gardenia. Change-Id: If4fdb9ae1e106ba15f2a073f592499e638e40c65 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28093 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Richard Spiegel
Patrick Georgi
parent
885d963391
commit
12f6d91a98
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@ -1,93 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* FCH ACPI lib
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision$ @e \$Date$
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*
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*/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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||||||
* modification, are permitted provided that the following conditions are met:
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||||||
* * Redistributions of source code must retain the above copyright
|
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||||||
* notice, this list of conditions and the following disclaimer.
|
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||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
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||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
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||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
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||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#include <check_for_wrapper.h>
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#ifndef _FCH_ACPILIB_H_
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#define _FCH_ACPILIB_H_
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///
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/// RSDP - ACPI 2.0 table RSDP
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///
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typedef struct _RSDP_HEADER {
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UINT64 Signature; ///< RSDP signature "RSD PTR"
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UINT8 CheckSum; ///< checksum of the first 20 bytes
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UINT8 OEMID[6]; ///< OEM ID
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UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
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UINT32 RsdtAddress; ///< physical address of RSDT
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UINT32 Length; ///< total length of RSDP (including extended part)
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UINT64 XsdtAddress; ///< physical address of XSDT
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UINT8 ExtendedCheckSum; ///< chechsum of whole table
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UINT8 Reserved[3]; ///< Reserved
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} RSDP_HEADER;
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///
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/// DESCRIPTION_HEADER - ACPI common table header
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///
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typedef struct _DESCRIPTION_HEADER {
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UINT32 Signature; ///< ACPI signature (4 ASCII characters)
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UINT32 Length; ///< Length of table, in bytes, including header
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UINT8 Revision; ///< ACPI Specification minor version #
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UINT8 CheckSum; ///< To make sum of entire table == 0
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UINT8 OemId[6]; ///< OEM identification
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UINT8 OemTableId[8]; ///< OEM table identification
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UINT32 OemRevision; ///< OEM revision number
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UINT32 CreatorId; ///< ASL compiler vendor ID
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UINT32 CreatorRevision; ///< ASL compiler revision number
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} DESCRIPTION_HEADER;
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///
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/// _AcpiRegWrite - ACPI MMIO register R/W structure
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///
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typedef struct _ACPI_REG_WRITE {
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UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
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UINT8 MmioReg; /// MmioReg : Register index
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UINT8 DataAndMask; /// DataANDMask : AND Register Data
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UINT8 DataOrMask; /// DataOrMask : Or Register Data
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} ACPI_REG_WRITE;
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VOID* AcpiLocateTable (IN UINT32 Signature);
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VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
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UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
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UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
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#endif
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@ -1,69 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* FCH BIOS Ram usage
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision$ @e \$Date$
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*
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*/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions are met:
|
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* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
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||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
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* documentation and/or other materials provided with the distribution.
|
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
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* its contributors may be used to endorse or promote products derived
|
|
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* from this software without specific prior written permission.
|
|
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*
|
|
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#include <check_for_wrapper.h>
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#ifndef _FCH_BIOS_RAM_USAGE_H_
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#define _FCH_BIOS_RAM_USAGE_H_
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#define RESTORE_MEMORY_CONTROLLER_START 0
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#define XHCI_REGISTER_BAR00 0xD0
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#define XHCI_REGISTER_BAR01 0xD1
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#define XHCI_REGISTER_BAR02 0xD2
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#define XHCI_REGISTER_BAR03 0xD3
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#define XHCI_REGISTER_04H 0xD4
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#define XHCI_REGISTER_0CH 0xD5
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#define XHCI_REGISTER_3CH 0xD6
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#define XHCI1_REGISTER_BAR00 0xE0
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#define XHCI1_REGISTER_BAR01 0xE1
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#define XHCI1_REGISTER_BAR02 0xE2
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#define XHCI1_REGISTER_BAR03 0xE3
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#define XHCI1_REGISTER_04H 0xE4
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#define XHCI1_REGISTER_0CH 0xE5
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#define XHCI1_REGISTER_3CH 0xE6
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#define RTC_WORKAROUND_DATA_START 0xF0
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#define BOOT_TIME_FLAG_SEC 0xF8
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#define BOOT_TIME_FLAG_INT19 0xFC
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#endif
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@ -1,408 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* FCH routine definition
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*
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*
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: FCH
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* @e \$Revision$ @e \$Date$
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*
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*/
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/*****************************************************************************
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*
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* Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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|
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* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
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* its contributors may be used to endorse or promote products derived
|
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* from this software without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#include <check_for_wrapper.h>
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#ifndef _FCH_DEF_H_
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#define _FCH_DEF_H_
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UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
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VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
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VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
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VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
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VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
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VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
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VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
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VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
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UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
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UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
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BOOLEAN FchCheckBR_ST (IN AMD_CONFIG_PARAMS *StdHeader);
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BOOLEAN FchCheckBR (IN AMD_CONFIG_PARAMS *StdHeader);
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BOOLEAN FchCheckST (IN AMD_CONFIG_PARAMS *StdHeader);
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BOOLEAN FchCheckCZ (IN AMD_CONFIG_PARAMS *StdHeader);
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BOOLEAN FchCheckPackageAM4 (IN AMD_CONFIG_PARAMS *StdHeader);
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UINT64 FchGetScratchFuse (IN AMD_CONFIG_PARAMS *StdHeader);
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VOID FchInitResetRequest (IN AMD_CONFIG_PARAMS *StdHeader);
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///
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/// Fch Ab Routines
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///
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/// Pei Phase
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///
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VOID FchInitResetAb (IN VOID* FchDataPtr);
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VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
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///
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/// Dxe Phase
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///
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VOID FchInitEnvAb (IN VOID* FchDataPtr);
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VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
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VOID FchInitMidAb (IN VOID* FchDataPtr);
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VOID FchInitLateAb (IN VOID* FchDataPtr);
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///
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/// Other Public Routines
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///
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VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
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BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
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VOID FchAbLateProgram (IN VOID* FchDataPtr);
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///
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/// Fch Pcie Routines
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///
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///
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/// Dxe Phase
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///
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VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
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///
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/// Fch Gpp Routines
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///
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///
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/// Common Gpp Routines
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///
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VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
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///
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/// Fch Azalia Routines
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///
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/// Pei Phase
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///
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VOID FchInitResetAzalia (IN VOID *FchDataPtr);
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///
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/// Dxe Phase
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///
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VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
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VOID FchInitMidAzalia (IN VOID *FchDataPtr);
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VOID FchInitLateAzalia (IN VOID *FchDataPtr);
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///
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/// Fch HwAcpi Routines
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///
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/// Pei Phase
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///
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VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
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VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
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VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
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///
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/// Dxe Phase
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///
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VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
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VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
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VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
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VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
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VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
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VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
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VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
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VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
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///
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/// Other Public Routines
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///
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VOID HpetInit (IN VOID *FchDataPtr);
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VOID MtC1eEnable (IN VOID *FchDataPtr);
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VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
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VOID StressResetModeLate (IN VOID *FchDataPtr);
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///
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/// Fch Hwm Routines
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///
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/// Pei Phase
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///
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VOID FchInitResetHwm (IN VOID* FchDataPtr);
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|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvHwm (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitMidHwm (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitLateHwm (IN VOID* FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID HwmInitRegister (IN VOID* FchDataPtr);
|
|
||||||
VOID FchECfancontrolservice (IN VOID* FchDataPtr);
|
|
||||||
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch EC Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetEc (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvEc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidEc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateEc (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Ir Routines
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvIr (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitMidIr (IN VOID* FchDataPtr);
|
|
||||||
VOID FchInitLateIr (IN VOID* FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch SATA Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitMidSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
VOID FchInitLateSata (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataIde (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataIde (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
|
|
||||||
VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
|
|
||||||
VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
|
|
||||||
VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
|
|
||||||
VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
|
|
||||||
VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
|
|
||||||
VOID SataBar5RegSet (IN VOID *FchDataPtr);
|
|
||||||
VOID SataSetPortGenMode (IN VOID *FchDataPtr);
|
|
||||||
VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
|
|
||||||
VOID FchProgramSataPhy (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// FCH USB Controller Public Function
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateUsb (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchEhciDebugPortService (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
|
|
||||||
VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
|
|
||||||
VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Sd Routines
|
|
||||||
///
|
|
||||||
VOID FchInitEnvSd (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSd (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSd (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
|
|
||||||
VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
///
|
|
||||||
/// Fch Spi Routines
|
|
||||||
///
|
|
||||||
/// Pei Phase
|
|
||||||
///
|
|
||||||
VOID FchInitResetSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Dxe Phase
|
|
||||||
///
|
|
||||||
VOID FchInitEnvSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateSpi (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitMidLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitLateLpc (IN VOID *FchDataPtr);
|
|
||||||
VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
|
|
||||||
///
|
|
||||||
/// Other Public Routines
|
|
||||||
///
|
|
||||||
VOID FchSpiUnlock (IN VOID *FchDataPtr);
|
|
||||||
VOID FchSpiLock (IN VOID *FchDataPtr);
|
|
||||||
VOID FchUsb3D3ColdCallback (IN VOID *FchDataPtr);
|
|
||||||
VOID FchUsb3D0Callback (IN VOID *FchDataPtr);
|
|
||||||
|
|
||||||
/*--------------------------- Documentation Pages ---------------------------*/
|
|
||||||
VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID TurnOffCG2 (OUT VOID);
|
|
||||||
VOID BackUpCG2 (OUT VOID);
|
|
||||||
VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
|
|
||||||
VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID AcLossControl (IN UINT8 AcLossControlValue);
|
|
||||||
VOID FchVgaInit (OUT VOID);
|
|
||||||
VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
|
|
||||||
VOID ValidateFchVariant (IN VOID *FchDataPtr);
|
|
||||||
VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
|
|
||||||
BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
|
|
||||||
VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
|
|
||||||
|
|
||||||
AGESA_STATUS
|
|
||||||
FchSpiTransfer (
|
|
||||||
IN UINT8 PrefixCode,
|
|
||||||
IN UINT8 Opcode,
|
|
||||||
IN OUT UINT8 *DataPtr,
|
|
||||||
IN UINT8 *AddressPtr,
|
|
||||||
IN UINT8 Length,
|
|
||||||
IN BOOLEAN WriteFlag,
|
|
||||||
IN BOOLEAN AddressFlag,
|
|
||||||
IN BOOLEAN DataFlag,
|
|
||||||
IN BOOLEAN FinishedFlag
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
FchConfigureSpiDeviceDummyCycle (
|
|
||||||
IN UINT32 DeviceID,
|
|
||||||
IN UINT8 SpiMode
|
|
||||||
);
|
|
||||||
|
|
||||||
UINT32
|
|
||||||
FchReadSpiId (
|
|
||||||
IN BOOLEAN Flag
|
|
||||||
);
|
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
FchPlatformSpiQe (
|
|
||||||
IN VOID *FchDataPtr
|
|
||||||
);
|
|
||||||
|
|
||||||
FCH_DATA_BLOCK*
|
|
||||||
FchInitLoadDataBlock (
|
|
||||||
IN FCH_INTERFACE *FchInterface,
|
|
||||||
IN AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
FCH_DATA_BLOCK*
|
|
||||||
FchInitEnvCreatePrivateData (
|
|
||||||
IN AMD_ENV_PARAMS *EnvParams
|
|
||||||
);
|
|
||||||
|
|
||||||
FCH_RESET_DATA_BLOCK*
|
|
||||||
FchInitResetLoadPrivateDefault (
|
|
||||||
IN AMD_RESET_PARAMS *ResetParams
|
|
||||||
);
|
|
||||||
|
|
||||||
VOID
|
|
||||||
RetrieveDataBlockFromInitReset (
|
|
||||||
IN FCH_DATA_BLOCK *FchParams
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
@ -110,9 +110,6 @@
|
||||||
#include "Fch.h"
|
#include "Fch.h"
|
||||||
#include "amdlib.h"
|
#include "amdlib.h"
|
||||||
#include "FchCommonCfg.h"
|
#include "FchCommonCfg.h"
|
||||||
#include "AcpiLib.h"
|
|
||||||
#include "FchDef.h"
|
|
||||||
#include "FchBiosRamUsage.h"
|
|
||||||
#include "AmdFch.h"
|
#include "AmdFch.h"
|
||||||
|
|
||||||
extern CONST BUILD_OPT_CFG UserOptions;
|
extern CONST BUILD_OPT_CFG UserOptions;
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue