hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
TRIVIAL. Rather than using the AGESA functions for PCI and MSR access, use the coreboot variants, which are cleaner and more readable. Change-Id: I4f24820606900e16f0d159df019f4560f1592489 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/5468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
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@ -26,9 +26,12 @@
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#include "BiosCallOuts.h"
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#include "PlatformGnbPcieComplex.h"
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#define __SIMPLE_DEVICE__
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <cbmem.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <device/device.h>
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#include <string.h>
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@ -79,53 +82,40 @@ VOID *AcpiIvrs = NULL;
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* L O C A L F U N C T I O N S
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*---------------------------------------------------------------------------------------
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*/
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UINT32
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agesawrapper_amdinitcpuio (
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VOID
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)
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uint32_t agesawrapper_amdinitcpuio(void)
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{
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AGESA_STATUS Status;
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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pci_devfn_t dev;
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msr_t msr;
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uint32_t reg32;
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dev = PCI_DEV(0, 0x18, 1);
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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pci_io_write_config32(dev, 0xf4, 1);
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/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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* Last address before processor local APIC at FEE00000
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*/
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
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PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
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PciData |= 1 << 7; /* set NP (non-posted) bit */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
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PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7));
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/* Lowest NP address is HPET at FED00000 */
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pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
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PciData = 0x00FECF00; /* last address before non-posted range */
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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pci_io_write_config32(dev, 0x8C, 0x00fecf00);
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msr = rdmsr(0xc001001a);
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reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */
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pci_io_write_config32(dev, 0x88, reg32);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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Status = AGESA_SUCCESS;
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return (UINT32)Status;
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pci_io_write_config32(dev, 0xc4, 0x0000f000);
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pci_io_write_config32(dev, 0xc0, 0x00000003);
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return AGESA_SUCCESS;
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}
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UINT32
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@ -81,7 +81,7 @@ UINT32 agesawrapper_amdinitpost (void);
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UINT32 agesawrapper_amdinitmid (void);
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UINT32 agesawrapper_amdreadeventlog (UINT8 HeapStatus);
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UINT32 agesawrapper_amdinitmmio (void);
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UINT32 agesawrapper_amdinitcpuio (void);
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uint32_t agesawrapper_amdinitcpuio (void);
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void *agesawrapper_getlateinitptr (int pick);
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UINT32 agesawrapper_amdlaterunaptask (UINT32 Func, UINT32 Data, void *ConfigPtr);
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UINT32 agesawrapper_amdS3Save(VOID);
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