soc/amd/stoneyridge: Add I2C devicetree support.
This commit establishes the stoneyridge implementation for i2c entries in the devicetree.cb file. BUG=b:72121803 Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/23405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -20,6 +20,7 @@
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#include <cpu/cpu.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/cpu.h>
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#include <soc/northbridge.h>
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#include <soc/pci_devs.h>
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@ -28,6 +29,10 @@
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#include <amdblocks/agesawrapper.h>
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#include <amdblocks/agesawrapper_call.h>
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/* Supplied by i2c.c */
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extern struct device_operations stoneyridge_i2c_mmio_ops;
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extern const char *i2c_acpi_name(const struct device *dev);
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struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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@ -79,6 +84,9 @@ static void enable_dev(device_t dev)
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dev->ops = &cpu_bus_ops;
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else if (dev->path.type == DEVICE_PATH_PCI)
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sb_enable(dev);
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else if (dev->path.type == DEVICE_PATH_MMIO)
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if (i2c_acpi_name(dev) != NULL)
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dev->ops = &stoneyridge_i2c_mmio_ops;
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}
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static void soc_init(void *chip_info)
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@ -19,11 +19,16 @@
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#include <stddef.h>
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#include <stdint.h>
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#include <commonlib/helpers.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/gpio.h>
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#include <arch/acpi_device.h>
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#define MAX_NODES 1
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#define MAX_DRAM_CH 1
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#define MAX_DIMMS_PER_CH 2
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#define STONEY_I2C_DEV_MAX 4
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struct soc_amd_stoneyridge_config {
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u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
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enum {
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@ -44,6 +49,8 @@ struct soc_amd_stoneyridge_config {
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/* Used if UMAMODE_SPECIFIED_SIZE is set. */
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size_t uma_size;
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struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
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};
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typedef struct soc_amd_stoneyridge_config config_t;
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@ -13,17 +13,87 @@
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <arch/acpigen.h>
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#include <console/console.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/iomap.h>
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#include "chip.h"
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#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x))
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#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0))
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#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1))
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#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2))
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#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3))
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/* Global to provide access to chip.c */
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const char *i2c_acpi_name(const struct device *dev);
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static const uintptr_t i2c_bus_address[] = {
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I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 0,
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I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 1,
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I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 2,
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I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 3,
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I2CA_BASE_ADDRESS,
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I2CB_BASE_ADDRESS,
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I2CC_BASE_ADDRESS,
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I2CD_BASE_ADDRESS,
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};
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uintptr_t dw_i2c_base_address(unsigned int bus)
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{
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return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0;
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}
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const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus,
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const struct device *dev)
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{
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const struct soc_amd_stoneyridge_config *config;
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
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__func__);
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return NULL;
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}
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if (bus >= ARRAY_SIZE(i2c_bus_address))
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return NULL;
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config = dev->chip_info;
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return &config->i2c[bus];
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}
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const char *i2c_acpi_name(const struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case I2CA_BASE_ADDRESS:
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return "I2CA";
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case I2CB_BASE_ADDRESS:
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return "I2CB";
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case I2CC_BASE_ADDRESS:
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return "I2CC";
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case I2CD_BASE_ADDRESS:
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return "I2CD";
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default:
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return NULL;
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}
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}
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int dw_i2c_soc_dev_to_bus(struct device *dev)
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{
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switch (dev->path.mmio.addr) {
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case I2CA_BASE_ADDRESS:
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return 0;
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case I2CB_BASE_ADDRESS:
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return 1;
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case I2CC_BASE_ADDRESS:
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return 2;
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case I2CD_BASE_ADDRESS:
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return 3;
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}
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return -1;
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}
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struct device_operations stoneyridge_i2c_mmio_ops = {
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/* TODO(teravest): Move I2C resource info here. */
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.scan_bus = scan_smbus,
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.acpi_name = i2c_acpi_name,
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.acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt,
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};
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