soc/amd/stoneyridge: Add I2C devicetree support.

This commit establishes the stoneyridge implementation for i2c entries
in the devicetree.cb file.

BUG=b:72121803

Change-Id: I0d923609bd8fce94c9aee401a5ae2811281b60e5
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Justin TerAvest 2018-01-24 14:23:12 -07:00 committed by Aaron Durbin
parent 949d666b5c
commit 13101a7be0
3 changed files with 89 additions and 4 deletions

View File

@ -20,6 +20,7 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/cpu.h> #include <soc/cpu.h>
#include <soc/northbridge.h> #include <soc/northbridge.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
@ -28,6 +29,10 @@
#include <amdblocks/agesawrapper.h> #include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h> #include <amdblocks/agesawrapper_call.h>
/* Supplied by i2c.c */
extern struct device_operations stoneyridge_i2c_mmio_ops;
extern const char *i2c_acpi_name(const struct device *dev);
struct device_operations cpu_bus_ops = { struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP, .read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP,
@ -79,6 +84,9 @@ static void enable_dev(device_t dev)
dev->ops = &cpu_bus_ops; dev->ops = &cpu_bus_ops;
else if (dev->path.type == DEVICE_PATH_PCI) else if (dev->path.type == DEVICE_PATH_PCI)
sb_enable(dev); sb_enable(dev);
else if (dev->path.type == DEVICE_PATH_MMIO)
if (i2c_acpi_name(dev) != NULL)
dev->ops = &stoneyridge_i2c_mmio_ops;
} }
static void soc_init(void *chip_info) static void soc_init(void *chip_info)

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@ -19,11 +19,16 @@
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <soc/gpio.h>
#include <arch/acpi_device.h>
#define MAX_NODES 1 #define MAX_NODES 1
#define MAX_DRAM_CH 1 #define MAX_DRAM_CH 1
#define MAX_DIMMS_PER_CH 2 #define MAX_DIMMS_PER_CH 2
#define STONEY_I2C_DEV_MAX 4
struct soc_amd_stoneyridge_config { struct soc_amd_stoneyridge_config {
u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH]; u8 spd_addr_lookup[MAX_NODES][MAX_DRAM_CH][MAX_DIMMS_PER_CH];
enum { enum {
@ -44,6 +49,8 @@ struct soc_amd_stoneyridge_config {
/* Used if UMAMODE_SPECIFIED_SIZE is set. */ /* Used if UMAMODE_SPECIFIED_SIZE is set. */
size_t uma_size; size_t uma_size;
struct dw_i2c_bus_config i2c[STONEY_I2C_DEV_MAX];
}; };
typedef struct soc_amd_stoneyridge_config config_t; typedef struct soc_amd_stoneyridge_config config_t;

View File

@ -13,17 +13,87 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <console/console.h>
#include <drivers/i2c/designware/dw_i2c.h> #include <drivers/i2c/designware/dw_i2c.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include "chip.h"
#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x))
#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0))
#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1))
#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2))
#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3))
/* Global to provide access to chip.c */
const char *i2c_acpi_name(const struct device *dev);
static const uintptr_t i2c_bus_address[] = { static const uintptr_t i2c_bus_address[] = {
I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 0, I2CA_BASE_ADDRESS,
I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 1, I2CB_BASE_ADDRESS,
I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 2, I2CC_BASE_ADDRESS,
I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * 3, I2CD_BASE_ADDRESS,
}; };
uintptr_t dw_i2c_base_address(unsigned int bus) uintptr_t dw_i2c_base_address(unsigned int bus)
{ {
return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0;
} }
const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus,
const struct device *dev)
{
const struct soc_amd_stoneyridge_config *config;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
__func__);
return NULL;
}
if (bus >= ARRAY_SIZE(i2c_bus_address))
return NULL;
config = dev->chip_info;
return &config->i2c[bus];
}
const char *i2c_acpi_name(const struct device *dev)
{
switch (dev->path.mmio.addr) {
case I2CA_BASE_ADDRESS:
return "I2CA";
case I2CB_BASE_ADDRESS:
return "I2CB";
case I2CC_BASE_ADDRESS:
return "I2CC";
case I2CD_BASE_ADDRESS:
return "I2CD";
default:
return NULL;
}
}
int dw_i2c_soc_dev_to_bus(struct device *dev)
{
switch (dev->path.mmio.addr) {
case I2CA_BASE_ADDRESS:
return 0;
case I2CB_BASE_ADDRESS:
return 1;
case I2CC_BASE_ADDRESS:
return 2;
case I2CD_BASE_ADDRESS:
return 3;
}
return -1;
}
struct device_operations stoneyridge_i2c_mmio_ops = {
/* TODO(teravest): Move I2C resource info here. */
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.scan_bus = scan_smbus,
.acpi_name = i2c_acpi_name,
.acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt,
};