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mb/google/octopus: Fix GPIO to GPE mappings in devicetree 

Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".

This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).

BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.

Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
This commit is contained in:
Furquan Shaikh 2018-06-07 15:27:14 -07:00 committed by Aaron Durbin
parent 9cd99a1524
commit 1313244ae7
2 changed files with 23 additions and 6 deletions
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15
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
View File

@ -29,9 +29,18 @@ chip soc/intel/apollolake
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_63_32"
# DW1 is used by:
# - GPIO_63 - H1_PCH_INT_ODL
# DW2 is used by:
# - GPIO_141 - EC_PCH_WAKE_ODL
# - GPIO_142 - TRACKPAD_INT2_1V8_ODL
# - GPIO_144 - PEN_EJECT_ODL
# DW3 is used by:
# - GPIO_117 - LTE_WAKE_ODL
# - GPIO_119 - WLAN_PCIE_WAKE_ODL
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
register "gpe0_dw3" = "PMC_GPE_N_63_32"
# PL1 override 8000 mW: Due to error in the energy calculation for
# current VR solution. Experiments show that SoC TDP max (6W) can
@ -122,7 +131,7 @@ chip soc/intel/apollolake
device pci 12.0 off end # - SATA
device pci 13.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_DW1_11"
register "wake" = "GPE0_DW3_11"
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)

14
src/mainboard/google/octopus/variants/bip/devicetree.cb
View File

@ -29,9 +29,17 @@ chip soc/intel/apollolake
# route, i.e., if this route changes then the affected GPE
# offset bits also need to be changed. This sets the PMC register
# GPE_CFG fields.
register "gpe0_dw1" = "PMC_GPE_N_63_32"
# DW1 is used by:
# - GPIO_63 - H1_PCH_INT_ODL
# DW2 is used by:
# - GPIO_141 - EC_PCH_WAKE_ODL
# - GPIO_142 - TRACKPAD_INT2_1V8_ODL
# DW3 is used by:
# - GPIO_117 - LTE_WAKE_ODL
# - GPIO_119 - WLAN_PCIE_WAKE_ODL
register "gpe0_dw1" = "PMC_GPE_NW_63_32"
register "gpe0_dw2" = "PMC_GPE_N_95_64"
register "gpe0_dw3" = "PMC_GPE_NW_31_0"
register "gpe0_dw3" = "PMC_GPE_N_63_32"
# PL1 override 8000 mW: Due to error in the energy calculation for
# current VR solution. Experiments show that SoC TDP max (6W) can
@ -122,7 +130,7 @@ chip soc/intel/apollolake
device pci 12.0 off end # - SATA
device pci 13.0 on
chip drivers/intel/wifi
register "wake" = "GPE0_DW1_11"
register "wake" = "GPE0_DW3_11"
device pci 00.0 on end
end
end # - PCIe-A 0 Onboard M2 Slot(Wifi)