nehalem: Replace video init.
Old video init just replayed the sequence. This one actually computes the values. Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5270 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Vladimir Serbinenko
parent
1b12ef1ac3
commit
131573056f
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@ -4049,6 +4049,11 @@
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#define PCH_LVDS 0xe1180
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#define LVDS_DETECTED (1 << 1)
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#define LVDS_BORDER_ENABLE (1 << 15)
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#define LVDS_PORT_ENABLE (1 << 31)
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#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
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#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
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#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
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/* vlv has 2 sets of panel control regs. */
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#define PIPEA_PP_STATUS 0x61200
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@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_ACPI_RESUME
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select EARLY_CBMEM_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
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config MAINBOARD_DIR
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string
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@ -35,6 +35,10 @@ chip northbridge/intel/nehalem
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register "gpu_panel_power_backlight_off_delay" = "2500"
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register "gpu_cpu_backlight" = "0x58d"
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register "gpu_pch_backlight" = "0x061a061a"
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register "gpu_use_spread_spectrum_clock" = "1"
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register "gpu_lvds_dual_channel" = "0"
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register "gpu_link_frequency_270_mhz" = "1"
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register "gpu_lvds_num_lanes" = "4"
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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@ -23,6 +23,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select VGA
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select INTEL_EDID
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if NORTHBRIDGE_INTEL_NEHALEM
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@ -38,5 +38,10 @@ struct northbridge_intel_nehalem_config {
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u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
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u32 gpu_pch_backlight; /* PCH Backlight PWM value */
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int gpu_use_spread_spectrum_clock;
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int gpu_lvds_dual_channel;
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int gpu_link_frequency_270_mhz;
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int gpu_lvds_num_lanes;
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};
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File diff suppressed because it is too large
Load Diff
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@ -28,6 +28,11 @@
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#include <device/pci_ops.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <drivers/intel/gma/edid.h>
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#include <drivers/intel/gma/i915.h>
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#include "chip.h"
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#include "nehalem.h"
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@ -545,16 +550,6 @@ static void gma_pm_init_pre_vbios(struct device *dev)
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gtt_write(0x6c024, reg32);
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}
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#include <pc80/vga.h>
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#include <pc80/vga_io.h>
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#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
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static void fake_vbios(void)
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{
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#include "fake_vbios.c"
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}
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#endif
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static void gma_pm_init_post_vbios(struct device *dev)
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{
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struct northbridge_intel_nehalem_config *conf = dev->chip_info;
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@ -620,6 +615,438 @@ static void gma_pm_init_post_vbios(struct device *dev)
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}
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}
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#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
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static void train_link(u32 mmio)
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{
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/* Clear interrupts. */
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write32(mmio + DEIIR, 0xffffffff);
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write32(mmio + 0x000f0018, 0x000000ff);
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write32(mmio + 0x000f1018, 0x000000ff);
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write32(mmio + 0x000f000c, 0x001a2050);
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write32(mmio + 0x00060100, 0x001c4000);
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write32(mmio + 0x00060100, 0x801c4000);
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write32(mmio + 0x000f000c, 0x801a2050);
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write32(mmio + 0x00060100, 0x801c4000);
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write32(mmio + 0x000f000c, 0x801a2050);
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mdelay(1);
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read32(mmio + 0x000f0014); // = 0x00000100
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write32(mmio + 0x000f0014, 0x00000100);
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write32(mmio + 0x00060100, 0x901c4000);
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write32(mmio + 0x000f000c, 0x901a2050);
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mdelay(1);
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read32(mmio + 0x000f0014); // = 0x00000600
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}
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static void power_port(u32 mmio)
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{
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read32(mmio + 0x000e1100); // = 0x00000000
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write32(mmio + 0x000e1100, 0x00000000);
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write32(mmio + 0x000e1100, 0x00010000);
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read32(mmio + 0x000e1100); // = 0x00010000
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read32(mmio + 0x000e1100); // = 0x00010000
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read32(mmio + 0x000e1100); // = 0x00000000
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write32(mmio + 0x000e1100, 0x00000000);
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read32(mmio + 0x000e1100); // = 0x00000000
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read32(mmio + 0x000e4200); // = 0x0000001c
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write32(mmio + 0x000e4210, 0x8004003e);
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write32(mmio + 0x000e4214, 0x80060002);
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write32(mmio + 0x000e4218, 0x01000000);
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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read32(mmio + 0x000e4210); // = 0x0144003e
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write32(mmio + 0x000e4210, 0x8074003e);
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read32(mmio + 0x000e4210); // = 0x5144003e
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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read32(mmio + 0x000e4210); // = 0x0144003e
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write32(mmio + 0x000e4210, 0x8074003e);
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read32(mmio + 0x000e4210); // = 0x5144003e
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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read32(mmio + 0x000e4210); // = 0x0144003e
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write32(mmio + 0x000e4210, 0x8074003e);
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read32(mmio + 0x000e4210); // = 0x5144003e
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read32(mmio + 0x000e4210); // = 0x5144003e
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write32(mmio + 0x000e4210, 0x5344003e);
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write32(mmio + 0x000e4f00, 0x0100030c);
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write32(mmio + 0x000e4f04, 0x00b8230c);
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write32(mmio + 0x000e4f08, 0x06f8930c);
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write32(mmio + 0x000e4f0c, 0x09f8e38e);
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write32(mmio + 0x000e4f10, 0x00b8030c);
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write32(mmio + 0x000e4f14, 0x0b78830c);
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write32(mmio + 0x000e4f18, 0x0ff8d3cf);
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write32(mmio + 0x000e4f1c, 0x01e8030c);
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write32(mmio + 0x000e4f20, 0x0ff863cf);
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write32(mmio + 0x000e4f24, 0x0ff803cf);
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write32(mmio + 0x000c4030, 0x00001000);
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read32(mmio + 0x000c4000); // = 0x00000000
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write32(mmio + 0x000c4030, 0x00001000);
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read32(mmio + 0x000e1150); // = 0x0000001c
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write32(mmio + 0x000e1150, 0x0000089c);
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write32(mmio + 0x000fcc00, 0x01986f00);
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write32(mmio + 0x000fcc0c, 0x01986f00);
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write32(mmio + 0x000fcc18, 0x01986f00);
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write32(mmio + 0x000fcc24, 0x01986f00);
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read32(mmio + 0x000c4000); // = 0x00000000
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read32(mmio + 0x000e1180); // = 0x40000002
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}
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static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
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u32 mmio, u32 physbase, u16 piobase, u32 lfb)
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{
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int i;
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u8 edid_data[128];
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struct edid edid;
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u32 hactive, vactive, right_border, bottom_border;
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int hpolarity, vpolarity;
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u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
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u32 candp1, candn;
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u32 best_delta = 0xffffffff;
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u32 target_frequency;
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u32 pixel_p1 = 1;
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u32 pixel_n = 1;
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u32 pixel_m1 = 1;
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u32 pixel_m2 = 1;
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u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
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u32 data_m1;
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u32 data_n1 = 0x00800000;
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u32 link_m1;
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u32 link_n1 = 0x00080000;
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write32(mmio + 0x00070080, 0x00000000);
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write32(mmio + DSPCNTR(0), 0x00000000);
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write32(mmio + 0x00071180, 0x00000000);
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write32(mmio + CPU_VGACNTRL, 0x0000298e | VGA_DISP_DISABLE);
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write32(mmio + 0x0007019c, 0x00000000);
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write32(mmio + 0x0007119c, 0x00000000);
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write32(mmio + 0x000fc008, 0x2c010000);
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write32(mmio + 0x000fc020, 0x2c010000);
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write32(mmio + 0x000fc038, 0x2c010000);
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write32(mmio + 0x000fc050, 0x2c010000);
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write32(mmio + 0x000fc408, 0x2c010000);
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write32(mmio + 0x000fc420, 0x2c010000);
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write32(mmio + 0x000fc438, 0x2c010000);
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write32(mmio + 0x000fc450, 0x2c010000);
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vga_gr_write(0x18, 0);
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write32(mmio + 0x00042004, 0x02000000);
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write32(mmio + 0x000fd034, 0x8421ffe0);
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/* Setup GTT. */
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for (i = 0; i < 0x2000; i++)
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{
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outl((i << 2) | 1, piobase);
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outl(physbase + (i << 12) + 1, piobase + 4);
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}
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vga_misc_write(0x67);
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const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
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0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
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0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
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0xff
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};
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vga_cr_write(0x11, 0);
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for (i = 0; i <= 0x18; i++)
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vga_cr_write(i, cr[i]);
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power_port(mmio);
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intel_gmbus_read_edid(mmio + PCH_GMBUS0, 3, 0x50, edid_data, 128);
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decode_edid(edid_data,
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sizeof(edid_data), &edid);
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/* Disable screen memory to prevent garbage from appearing. */
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vga_sr_write(1, vga_sr_read(1) | 0x20);
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hactive = edid.x_resolution;
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vactive = edid.y_resolution;
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right_border = edid.hborder;
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bottom_border = edid.vborder;
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hpolarity = (edid.phsync == '-');
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vpolarity = (edid.pvsync == '-');
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vsync = edid.vspw;
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hsync = edid.hspw;
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vblank = edid.vbl;
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hblank = edid.hbl;
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hfront_porch = edid.hso;
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vfront_porch = edid.vso;
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target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
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: (2 * edid.pixel_clock);
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#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
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vga_textmode_init();
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#else
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vga_sr_write(1, 1);
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vga_sr_write(0x2, 0xf);
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vga_sr_write(0x3, 0x0);
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vga_sr_write(0x4, 0xe);
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vga_gr_write(0, 0x0);
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vga_gr_write(1, 0x0);
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vga_gr_write(2, 0x0);
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vga_gr_write(3, 0x0);
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vga_gr_write(4, 0x0);
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vga_gr_write(5, 0x0);
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vga_gr_write(6, 0x5);
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vga_gr_write(7, 0xf);
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vga_gr_write(0x10, 0x1);
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vga_gr_write(0x11, 0);
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edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
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write32(mmio + DSPCNTR(0), DISPPLANE_BGRX888);
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write32(mmio + DSPADDR(0), 0);
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write32(mmio + DSPSTRIDE(0), edid.bytes_per_line);
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write32(mmio + DSPSURF(0), 0);
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for (i = 0; i < 0x100; i++)
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write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101);
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#endif
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/* Find suitable divisors. */
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for (candp1 = 1; candp1 <= 8; candp1++) {
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for (candn = 5; candn <= 10; candn++) {
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u32 cur_frequency;
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u32 m; /* 77 - 131. */
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u32 denom; /* 35 - 560. */
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u32 current_delta;
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denom = candn * candp1 * 7;
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/* Doesnt overflow for up to
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5000000 kHz = 5 GHz. */
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m = (target_frequency * denom + 60000) / 120000;
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if (m < 77 || m > 131)
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continue;
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cur_frequency = (120000 * m) / denom;
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if (target_frequency > cur_frequency)
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current_delta = target_frequency - cur_frequency;
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else
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current_delta = cur_frequency - target_frequency;
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if (best_delta > current_delta) {
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best_delta = current_delta;
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pixel_n = candn;
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pixel_p1 = candp1;
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pixel_m2 = ((m + 3) % 5) + 7;
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pixel_m1 = (m - pixel_m2) / 5;
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}
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}
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}
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if (best_delta == 0xffffffff) {
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printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
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return;
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}
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link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
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data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
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/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4));
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printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
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hactive, vactive);
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printk(BIOS_DEBUG, "Borders %d x %d\n",
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right_border, bottom_border);
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printk(BIOS_DEBUG, "Blank %d x %d\n",
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hblank, vblank);
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printk(BIOS_DEBUG, "Sync %d x %d\n",
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hsync, vsync);
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printk(BIOS_DEBUG, "Front porch %d x %d\n",
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hfront_porch, vfront_porch);
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printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
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? "Spread spectrum clock\n" : "DREF clock\n"));
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printk(BIOS_DEBUG,
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info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
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printk(BIOS_DEBUG, "Polarities %d, %d\n",
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hpolarity, vpolarity);
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printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
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data_m1, data_n1);
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printk(BIOS_DEBUG, "Link frequency %d kHz\n",
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link_frequency);
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printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
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link_m1, link_n1);
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printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
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pixel_n, pixel_m1, pixel_m2, pixel_p1);
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printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
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120000 * (5 * pixel_m1 + pixel_m2) / pixel_n
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/ (pixel_p1 * 7));
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write32(mmio + PCH_LVDS,
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(hpolarity << 20) | (vpolarity << 21)
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| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
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| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
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| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
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| LVDS_DETECTED);
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write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
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write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock
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? 0x1002 : 0x400));
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mdelay(1);
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write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
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| (read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
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write32(mmio + _PCH_FP0(0),
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((pixel_n - 2) << 16)
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| ((pixel_m1 - 2) << 8) | pixel_m2);
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write32(mmio + _PCH_DPLL(0),
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DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
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| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
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: DPLLB_LVDS_P2_CLOCK_DIV_14)
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| (0x10000 << (pixel_p1 - 1))
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| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
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| (0x1 << (pixel_p1 - 1)));
|
||||
mdelay(1);
|
||||
write32(mmio + _PCH_DPLL(0),
|
||||
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
|
||||
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
|
||||
: DPLLB_LVDS_P2_CLOCK_DIV_14)
|
||||
| (0x10000 << (pixel_p1 - 1))
|
||||
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
|
||||
| (0x1 << (pixel_p1 - 1)));
|
||||
/* Re-lock the registers. */
|
||||
write32(mmio + PCH_PP_CONTROL,
|
||||
(read32(mmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
|
||||
|
||||
write32(mmio + PCH_LVDS,
|
||||
(hpolarity << 20) | (vpolarity << 21)
|
||||
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
|
||||
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
|
||||
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
|
||||
| LVDS_DETECTED);
|
||||
|
||||
write32(mmio + HTOTAL(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + HBLANK(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive + right_border - 1));
|
||||
write32(mmio + HSYNC(0),
|
||||
((hactive + right_border + hfront_porch + hsync - 1) << 16)
|
||||
| (hactive + right_border + hfront_porch - 1));
|
||||
|
||||
write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive + bottom_border - 1));
|
||||
write32(mmio + VSYNC(0),
|
||||
(vactive + bottom_border + vfront_porch + vsync - 1)
|
||||
| (vactive + bottom_border + vfront_porch - 1));
|
||||
|
||||
write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
|
||||
|
||||
write32(mmio + PF_WIN_POS(0), 0);
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + PIPESRC(0), ((hactive - 1) << 16) | (vactive - 1));
|
||||
write32(mmio + PF_CTL(0),0);
|
||||
write32(mmio + PF_WIN_SZ(0), 0);
|
||||
#else
|
||||
write32(mmio + PIPESRC(0), (639 << 16) | 399);
|
||||
write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
|
||||
write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16));
|
||||
#endif
|
||||
|
||||
mdelay(1);
|
||||
|
||||
write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
|
||||
write32(mmio + PIPE_DATA_N1(0), data_n1);
|
||||
write32(mmio + PIPE_LINK_M1(0), link_m1);
|
||||
write32(mmio + PIPE_LINK_N1(0), link_n1);
|
||||
|
||||
write32(mmio + 0x000f000c, 0x00002040);
|
||||
mdelay(1);
|
||||
write32(mmio + 0x000f000c, 0x00002050);
|
||||
write32(mmio + 0x00060100, 0x00044000);
|
||||
mdelay(1);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
|
||||
write32(mmio + 0x000f0008, 0x00000040);
|
||||
write32(mmio + 0x000f000c, 0x00022050);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e | VGA_DISP_DISABLE);
|
||||
#else
|
||||
write32(mmio + CPU_VGACNTRL, 0x20298e);
|
||||
#endif
|
||||
train_link(mmio);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
|
||||
mdelay(1);
|
||||
#endif
|
||||
|
||||
write32(mmio + TRANS_HTOTAL(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive - 1));
|
||||
write32(mmio + TRANS_HBLANK(0),
|
||||
((hactive + right_border + hblank - 1) << 16)
|
||||
| (hactive + right_border - 1));
|
||||
write32(mmio + TRANS_HSYNC(0),
|
||||
((hactive + right_border + hfront_porch + hsync - 1) << 16)
|
||||
| (hactive + right_border + hfront_porch - 1));
|
||||
|
||||
write32(mmio + TRANS_VTOTAL(0),
|
||||
((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive - 1));
|
||||
write32(mmio + TRANS_VBLANK(0),
|
||||
((vactive + bottom_border + vblank - 1) << 16)
|
||||
| (vactive + bottom_border - 1));
|
||||
write32(mmio + TRANS_VSYNC(0),
|
||||
(vactive + bottom_border + vfront_porch + vsync - 1)
|
||||
| (vactive + bottom_border + vfront_porch - 1));
|
||||
|
||||
write32(mmio + 0x00060100, 0xb01c4000);
|
||||
write32(mmio + 0x000f000c, 0xb01a2050);
|
||||
mdelay(1);
|
||||
write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
| TRANS_STATE_MASK
|
||||
#endif
|
||||
);
|
||||
write32(mmio + PCH_LVDS,
|
||||
LVDS_PORT_ENABLE
|
||||
| (hpolarity << 20) | (vpolarity << 21)
|
||||
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
|
||||
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
|
||||
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
|
||||
| LVDS_DETECTED);
|
||||
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
|
||||
mdelay(1);
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
|
||||
| PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
printk (BIOS_DEBUG, "waiting for panel powerup\n");
|
||||
while (1) {
|
||||
u32 reg32;
|
||||
reg32 = read32(mmio + PCH_PP_STATUS);
|
||||
if (((reg32 >> 28) & 3) == 0)
|
||||
break;
|
||||
}
|
||||
printk (BIOS_DEBUG, "panel powered up\n");
|
||||
|
||||
write32(mmio + PCH_PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
|
||||
|
||||
/* Enable screen memory. */
|
||||
vga_sr_write(1, vga_sr_read(1) & ~0x20);
|
||||
|
||||
/* Clear interrupts. */
|
||||
write32(mmio + DEIIR, 0xffffffff);
|
||||
write32(mmio + SDEIIR, 0xffffffff);
|
||||
|
||||
#if IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
|
||||
memset ((void *) lfb, 0, edid.x_resolution * edid.y_resolution * 4);
|
||||
set_vbe_mode_info_valid(&edid, lfb);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static void gma_func0_init(struct device *dev)
|
||||
{
|
||||
u32 reg32;
|
||||
|
|
@ -636,8 +1063,23 @@ static void gma_func0_init(struct device *dev)
|
|||
/* PCI Init, will run VBIOS */
|
||||
pci_dev_init(dev);
|
||||
#else
|
||||
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
|
||||
fake_vbios();
|
||||
u32 physbase;
|
||||
struct northbridge_intel_nehalem_config *conf = dev->chip_info;
|
||||
struct resource *lfb_res;
|
||||
struct resource *pio_res;
|
||||
|
||||
lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2);
|
||||
pio_res = find_resource(dev, PCI_BASE_ADDRESS_4);
|
||||
|
||||
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
|
||||
|
||||
if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base
|
||||
&& lfb_res && lfb_res->base) {
|
||||
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
|
||||
gtt_res->base);
|
||||
intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
|
||||
lfb_res->base);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Linux relies on VBT for panel info. */
|
||||
|
|
|
|||
Loading…
Reference in New Issue