nb/intel/pineview: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR register. The `length` bitfield was set to 0, so assume 256 busses. Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Angel Pons
parent
b274ec73ab
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1318ab475d
7 changed files with 22 additions and 62 deletions
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@ -23,6 +23,10 @@ config VGA_BIOS_ID
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config MMCONF_BASE_ADDRESS
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default 0xe0000000
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config MMCONF_BUS_NUMBER
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int
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default 256
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config SMM_RESERVED_SIZE
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hex
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default 0x80000
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@ -2,21 +2,12 @@
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#include <acpi/acpigen.h>
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#include <acpi/acpi.h>
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#include <commonlib/helpers.h>
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#include <device/device.h>
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#include <northbridge/intel/pineview/pineview.h>
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#include <types.h>
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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u32 length, pciexbar;
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if (!decode_pcie_bar(&pciexbar, &length))
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return current;
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const int max_buses = length / MiB;
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0,
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max_buses - 1);
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current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
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CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
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return current;
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}
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@ -17,7 +17,7 @@ Device (PDRC)
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Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
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Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
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Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000)
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Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
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Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
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Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */
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@ -1,14 +1,23 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/bootblock.h>
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#include <assert.h>
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#include <device/pci_ops.h>
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#include <types.h>
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#include "pineview.h"
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#define MMCONF_256_BUSSES 16
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#define ENABLE 1
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static uint32_t encode_pciexbar_length(void)
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{
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switch (CONFIG_MMCONF_BUS_NUMBER) {
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case 256: return 0 << 1;
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case 128: return 1 << 1;
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case 64: return 2 << 1;
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default: return dead_code_t(uint32_t);
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}
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}
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void bootblock_early_northbridge_init(void)
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{
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pci_io_write_config32(HOST_BRIDGE, PCIEXBAR,
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CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE);
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const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
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pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
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}
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@ -15,43 +15,6 @@
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#include <cpu/intel/smm_reloc.h>
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#include <stdint.h>
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int decode_pcie_bar(u32 *const base, u32 *const len)
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{
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*base = 0;
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*len = 0;
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const struct {
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u16 num_buses;
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u32 addr_mask;
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} busmask[] = {
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{256, 0xf0000000},
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{128, 0xf8000000},
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{64, 0xfc000000},
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{0, 0},
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};
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const u32 pciexbar_reg = pci_read_config32(HOST_BRIDGE, PCIEXBAR);
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/* MMCFG not supported or not enabled */
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if (!(pciexbar_reg & (1 << 0))) {
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printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
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return 0;
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}
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const u32 index = (pciexbar_reg >> 1) & 3;
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const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
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const int max_buses = busmask[index].num_buses;
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if (!pciexbar) {
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printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");
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return 0;
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}
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*base = pciexbar;
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*len = max_buses * MiB;
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return 1;
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}
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/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
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u32 decode_igd_memory_size(const u32 gms)
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{
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@ -42,7 +42,7 @@ static void mch_domain_read_resources(struct device *dev)
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{
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u64 tom, touud;
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u32 tomk, tolud, tseg_sizek;
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u32 pcie_config_base, pcie_config_size, cbmem_topk, delta_cbmem;
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u32 cbmem_topk, delta_cbmem;
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u16 index;
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const u32 top32memk = 4 * (GiB / KiB);
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@ -115,13 +115,7 @@ static void mch_domain_read_resources(struct device *dev)
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(touud - top32memk) / KiB);
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}
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if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) {
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printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n",
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pcie_config_base, pcie_config_size);
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fixed_mem_resource(dev, index++, pcie_config_base / KiB,
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pcie_config_size / KiB, IORESOURCE_RESERVE);
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}
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mmconf_resource(dev, index++);
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add_fixed_resources(dev, index);
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}
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@ -68,7 +68,6 @@
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void pineview_early_init(void);
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u32 decode_igd_memory_size(const u32 gms);
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u32 decode_igd_gtt_size(const u32 gsm);
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int decode_pcie_bar(u32 *const base, u32 *const len);
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/* Mainboard romstage callback functions */
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void get_mb_spd_addrmap(u8 *spd_addr_map);
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