superio/ite/it8720f: add new IT8720F Super I/O
This device is extremely similar to the IT8718F, so support is based on existing support for the IT8718F. The CIR device is only detected by Linux/Windows from the ACPI tables, so ACPI support is extended from the IT8783E/F (for ACPI). This Super I/O is used on the Foxconn G41S-K. Tested, working: * Serial port 1 * Environment controller - Temperature monitoring - Voltage monitoring - Fan control (automatic and manual) * PS/2 keyboard and mouse Appears, OS driver loads, but otherwise untested: * Serial port 2 * Consumer IR Untested: * Floppy controller * Parallel port * GPIO Change-Id: Ib9a6fe91a772d78f4d122a6c516feff8658ada0a Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-on: https://review.coreboot.org/20026 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Samuel Holland
Martin Roth
parent
da8ca6561f
commit
1318ea600b
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@ -23,6 +23,7 @@ subdirs-y += it8671f
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subdirs-y += it8712f
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subdirs-y += it8716f
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subdirs-y += it8718f
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subdirs-y += it8720f
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subdirs-y += it8721f
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subdirs-y += it8728f
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subdirs-y += it8772f
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@ -0,0 +1,23 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Ronald G. Minnich
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## Copyright (C) 2014 Edward O'Callaghan <eocallaghan@alterapraxis.com>
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## Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SUPERIO_ITE_IT8720F
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bool
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select SUPERIO_ITE_COMMON_ROMSTAGE
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select SUPERIO_ITE_ENV_CTRL
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select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG
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select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2
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@ -0,0 +1,18 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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## Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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ramstage-$(CONFIG_SUPERIO_ITE_IT8720F) += superio.c
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@ -0,0 +1,211 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Christoph Grenz <christophg+cb@grenz-bonn.de>
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* Copyright (C) 2013, 2016 secunet Security Networks AG
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* Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Include this file into a mainboard's DSDT _SB device tree and it will
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* expose the IT8720F SuperIO and some of its functionality.
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*
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* It allows the change of IO ports, IRQs and DMA settings on logical
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* devices, disabling and reenabling logical devices.
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*
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* LDN State
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* 0x0 FDC Not implemented
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* 0x1 SP1 Implemented, untested
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* 0x2 SP2 Implemented, untested
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* 0x3 PP Not implemented
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* 0x4 EC Implemented, untested
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* 0x5 KBCK Implemented, untested
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* 0x6 KBCM Implemented, untested
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* 0x7 GPIO Implemented, untested
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* 0xa CIR Implemented, untested
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*
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* Controllable through preprocessor defines:
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* SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
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* SUPERIO_PNP_BASE I/O address of the first PnP configuration register
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* IT8720F_SHOW_SP1 If defined, Serial Port 1 will be exposed.
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* IT8720F_SHOW_SP2 If defined, Serial Port 2 will be exposed.
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* IT8720F_SHOW_EC If defined, the Environment Controller will be exposed.
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* IT8720F_SHOW_KBCK If defined, the Keyboard Controller will be exposed.
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* IT8720F_SHOW_KBCM If defined, PS/2 mouse support will be exposed.
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* IT8720F_SHOW_GPIO If defined, GPIO support will be exposed.
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* IT8720F_SHOW_CIR If defined, Consumer IR support will be exposed.
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*/
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#undef SUPERIO_CHIP_NAME
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#define SUPERIO_CHIP_NAME IT8720F
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#include <superio/acpi/pnp.asl>
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#undef PNP_DEFAULT_PSC
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#define PNP_DEFAULT_PSC Return (0) /* no power management */
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#define CONFIGURE_CONTROL CCTL
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Device(SUPERIO_DEV) {
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Name (_HID, EisaId("PNP0A05"))
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Name (_STR, Unicode("ITE IT8720F Super I/O"))
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Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
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/* SuperIO configuration ports */
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OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
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Field (CREG, ByteAcc, NoLock, Preserve)
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{
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PNP_ADDR_REG, 8,
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PNP_DATA_REG, 8
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}
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IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
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{
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Offset (0x02),
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CONFIGURE_CONTROL, 8, /* Global configure control */
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Offset (0x07),
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PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
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Offset (0x30),
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PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
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Offset (0x60),
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PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
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PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
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Offset (0x62),
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PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
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PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
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Offset (0x64),
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PNP_IO2_HIGH_BYTE, 8, /* Third I/O port base - high byte */
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PNP_IO2_LOW_BYTE, 8, /* Third I/O port base - low byte */
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Offset (0x70),
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PNP_IRQ0, 8, /* First IRQ */
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}
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Method (_CRS)
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{
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/* Announce the used I/O ports to the OS */
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Return (ResourceTemplate () {
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IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
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})
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}
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#undef PNP_ENTER_MAGIC_1ST
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#undef PNP_ENTER_MAGIC_2ND
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#undef PNP_ENTER_MAGIC_3RD
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#undef PNP_ENTER_MAGIC_4TH
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#undef PNP_EXIT_MAGIC_1ST
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#undef PNP_EXIT_SPECIAL_REG
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#undef PNP_EXIT_SPECIAL_VAL
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#define PNP_ENTER_MAGIC_1ST 0x87
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#define PNP_ENTER_MAGIC_2ND 0x01
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#define PNP_ENTER_MAGIC_3RD 0x55
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#if SUPERIO_PNP_BASE == 0x2e
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#define PNP_ENTER_MAGIC_4TH 0x55
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#else
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#define PNP_ENTER_MAGIC_4TH 0xaa
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#endif
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#define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL
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#define PNP_EXIT_SPECIAL_VAL 0x02
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#include <superio/acpi/pnp_config.asl>
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#ifdef IT8720F_SHOW_SP1
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 1
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8720F_SHOW_SP2
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#undef SUPERIO_UART_LDN
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#undef SUPERIO_UART_DDN
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#undef SUPERIO_UART_PM_REG
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#undef SUPERIO_UART_PM_VAL
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#undef SUPERIO_UART_PM_LDN
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#define SUPERIO_UART_LDN 2
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#include <superio/acpi/pnp_uart.asl>
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#endif
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#ifdef IT8720F_SHOW_EC
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 4
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IO1 0x08, 0x04
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#define SUPERIO_PNP_IRQ0
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef IT8720F_SHOW_KBC
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#undef SUPERIO_KBC_LDN
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#undef SUPERIO_KBC_PS2M
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#undef SUPERIO_KBC_PS2LDN
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#define SUPERIO_KBC_LDN 5
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#ifdef IT8720F_SHOW_PS2M
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#define SUPERIO_KBC_PS2LDN 6
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#endif
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#include <superio/acpi/pnp_kbc.asl>
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#endif
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#ifdef IT8720F_SHOW_GPIO
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_LDN 7
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IO1 0x08, 0x08
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#define SUPERIO_PNP_IO2 0x08, 0x08
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#include <superio/acpi/pnp_generic.asl>
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#endif
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#ifdef IT8720F_SHOW_CIR
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#undef SUPERIO_PNP_HID
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#undef SUPERIO_PNP_LDN
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#undef SUPERIO_PNP_DDN
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#undef SUPERIO_PNP_PM_REG
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#undef SUPERIO_PNP_PM_VAL
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#undef SUPERIO_PNP_PM_LDN
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#undef SUPERIO_PNP_IO0
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#undef SUPERIO_PNP_IO1
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#undef SUPERIO_PNP_IO2
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#undef SUPERIO_PNP_IRQ0
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#undef SUPERIO_PNP_IRQ1
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#undef SUPERIO_PNP_DMA
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#define SUPERIO_PNP_HID "ITE8704"
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#define SUPERIO_PNP_LDN 10
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#define SUPERIO_PNP_IO0 0x08, 0x08
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#define SUPERIO_PNP_IRQ0
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#include <superio/acpi/pnp_generic.asl>
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#endif
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}
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 secunet Security Networks AG
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* Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SUPERIO_ITE_IT8720F_CHIP_H
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#define SUPERIO_ITE_IT8720F_CHIP_H
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#include <superio/ite/common/env_ctrl_chip.h>
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struct superio_ite_it8720f_config {
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struct ite_ec_config ec;
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};
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#endif /* SUPERIO_ITE_IT8720F_CHIP_H */
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@ -0,0 +1,33 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
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* Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SUPERIO_ITE_IT8720F_H
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#define SUPERIO_ITE_IT8720F_H
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/* Logical Device Numbers (LDN). */
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#define IT8720F_FDC 0x00 /* Floppy */
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#define IT8720F_SP1 0x01 /* Serial port 1 */
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#define IT8720F_SP2 0x02 /* Serial port 2 */
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#define IT8720F_PP 0x03 /* Parallel port */
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#define IT8720F_EC 0x04 /* Environment controller */
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#define IT8720F_KBCK 0x05 /* PS/2 keyboard */
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#define IT8720F_KBCM 0x06 /* PS/2 mouse */
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#define IT8720F_GPIO 0x07 /* GPIO (including SPI flash interface) */
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#define IT8720F_CIR 0x0a /* Consumer IR */
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#endif /* SUPERIO_ITE_IT8720F_H */
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@ -0,0 +1,101 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 secunet Security Networks AG
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* Copyright (C) 2017 Samuel Holland <samuel@sholland.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pnp.h>
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#include <pc80/keyboard.h>
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#include <superio/ite/common/env_ctrl.h>
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#include <superio/conf_mode.h>
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#include "chip.h"
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#include "it8720f.h"
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static void it8720f_init(struct device *dev)
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{
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const struct superio_ite_it8720f_config *conf;
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const struct resource *res;
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if (!dev->enabled)
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return;
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switch (dev->path.pnp.device) {
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case IT8720F_EC:
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conf = dev->chip_info;
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res = find_resource(dev, PNP_IDX_IO0);
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if (!conf || !res)
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break;
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ite_ec_init(res->base, &conf->ec);
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break;
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case IT8720F_KBCK:
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pc_keyboard_init(NO_AUX_DEVICE);
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break;
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default:
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break;
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}
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}
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static struct device_operations ops = {
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.read_resources = pnp_read_resources,
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.set_resources = pnp_set_resources,
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.enable_resources = pnp_enable_resources,
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.enable = pnp_enable,
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.init = it8720f_init,
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.ops_pnp_mode = &pnp_conf_mode_870155_aa,
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};
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static struct pnp_info pnp_dev_info[] = {
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{ &ops, IT8720F_FDC,
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PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0 | PNP_MSC1,
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{0x0ff8, 0}, },
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{ &ops, IT8720F_SP1,
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PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
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{0x0ff8, 0}, },
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{ &ops, IT8720F_SP2,
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PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1,
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{0x0ff8, 0}, },
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{ &ops, IT8720F_PP,
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PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | PNP_MSC0,
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{0x0ff8, 0}, {0x0ffc, 0}, },
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{ &ops, IT8720F_EC,
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PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
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PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6,
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{0x0ff8, 0}, {0x0ffc, 0}, },
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{ &ops, IT8720F_KBCK,
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PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0,
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{0x0fff, 0}, {0x0fff, 0}, },
|
||||
{ &ops, IT8720F_KBCM,
|
||||
PNP_IRQ0 | PNP_MSC0, },
|
||||
{ &ops, IT8720F_GPIO,
|
||||
PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_MSC0 | PNP_MSC1 | PNP_MSC2 |
|
||||
PNP_MSC3 | PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 |
|
||||
PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB | PNP_MSCD | PNP_MSCE,
|
||||
{0x0ff8, 0}, {0x0ff8, 0}, {0x0ff8, 0}, },
|
||||
{ &ops, IT8720F_CIR,
|
||||
PNP_IO0 | PNP_IRQ0 | PNP_MSC0,
|
||||
{0x0ff8, 0}, },
|
||||
};
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
pnp_enable_devices(dev, &pnp_ops,
|
||||
ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
|
||||
}
|
||||
|
||||
struct chip_operations superio_ite_it8720f_ops = {
|
||||
CHIP_NAME("ITE IT8720F Super I/O")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
Loading…
Reference in New Issue