mb/google/nissa/var/anraggar: Change code style for register usb2_ports
Change code style to be compatible with Nissa's format: register "option" = "{ [0] = value /* comment */ ... }" to register "option[0]" = "value" /* comment */ BUG=none TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I60659bd44813173f9b984216473a0919c5f331b8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
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@ -408,16 +408,14 @@ chip soc/intel/alderlake
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end
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end
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device ref xhci on
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register "usb2_ports" = "{
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[0] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C MB (7.5 inch) */
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[1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C DB (7.1 inch) */
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[2] = USB2_PORT_MID(OC_SKIP), /* Type-A MB (6.4 inch) */
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[3] = USB2_PORT_MID(OC_SKIP), /* Type-A DB (6.2 inch) */
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[4] = USB2_PORT_SHORT(OC_SKIP), /* LTE (3.3 inch) */
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[5] = USB2_PORT_SHORT(OC_SKIP), /* UFC (3.7 inch) */
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[7] = USB2_PORT_SHORT(OC_SKIP), /* Bluetooth port for PCIe WLAN (2.5 inch) */
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[9] = USB2_PORT_SHORT(OC_SKIP), /* Bluetooth port for CNVi WLAN */
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}"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C MB (7.5 inch)
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C DB (7.1 inch)
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register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MB (6.4 inch)
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register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A DB (6.2 inch)
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register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" # LTE (3.3 inch)
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register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" # UFC (3.7 inch)
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register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for PCIe WLAN (2.5 inch)
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register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" # Bluetooth port for CNVi WLAN
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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chip drivers/usb/acpi
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