HWM: Nuvoton W83795G/ADG HWM support
Supermicro H8QGI-F 1 Unit Chassis contain 9 system Fans, they are controled by a separate W83795G Hardware Monitor chip. This patch adds Nuvoton W83795G/ADG HWM support. Change-Id: I8756f5ed02dc2fa0884cde36e51451fd8aacee27 Signed-off-by: Kerry Sheh <kerry.she@amd.com> Signed-off-by: Kerry Sheh <shekairui@gmail.com> Reviewed-on: http://review.coreboot.org/569 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh
Marc Jones
parent
a3f060748b
commit
134d8a94de
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@ -4,3 +4,4 @@ source src/drivers/i2c/adt7463/Kconfig
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source src/drivers/i2c/i2cmux/Kconfig
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source src/drivers/i2c/i2cmux2/Kconfig
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source src/drivers/i2c/lm63/Kconfig
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source src/drivers/i2c/w83795/Kconfig
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@ -4,3 +4,4 @@ subdirs-y += adt7463
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subdirs-y += i2cmux
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subdirs-y += i2cmux2
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subdirs-y += lm63
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subdirs-y += w83795
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@ -0,0 +1,2 @@
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config DRIVERS_I2C_W83795
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bool
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@ -0,0 +1 @@
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driver-$(CONFIG_DRIVERS_I2C_W83795) += w83795.c
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@ -0,0 +1,4 @@
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extern struct chip_operations drivers_i2c_w83795_ops;
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struct drivers_i2c_w83795_config {
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};
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@ -0,0 +1,261 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <device/device.h>
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#include "southbridge/amd/cimx/sb700/smbus.h" /*SMBUS_IO_BASE*/
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#include "w83795.h"
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static u32 w83795_set_bank(u8 bank)
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{
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return do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, W83795_REG_BANKSEL, bank);
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}
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static u8 w83795_read(u16 reg)
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{
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u32 ret;
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ret = w83795_set_bank(reg >> 8);
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if (ret < 0) {
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printk(BIOS_DEBUG, "read faild to set bank %x\n", reg >> 8);
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return -1;
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}
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ret = do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff);
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return ret;
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}
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static u8 w83795_write(u16 reg, u8 value)
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{
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u32 err;
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err = w83795_set_bank(reg >> 8);
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if (err < 0) {
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printk(BIOS_DEBUG, "write faild to set bank %x\n", reg >> 8);
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return -1;
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}
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err = do_smbus_write_byte(SMBUS_IO_BASE, W83795_DEV, reg & 0xff, value);
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return err;
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}
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/*
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* Enable Digital Temperature Sensor
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*/
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static void w83795_dts_enable(u8 dts_src)
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{
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u8 val;
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/* DIS */
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val = w83795_read(W83795_REG_DTSC);
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val |= (dts_src & 0x01);
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w83795_write(W83795_REG_DTSC, val);
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/* DTSE */
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val = w83795_read(W83795_REG_DTSE);
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val |= 0xFF;
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w83795_write(W83795_REG_DTSE, val);
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/* store bank3 regs first before enable DTS */
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/*
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* TD/TR1-4 termal diode by default
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* 0x00 Disable
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* 0x01 thermistors on motherboard
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* 0x10 different mode voltage
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* 0x11 CPU internal thermal diode output
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*
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* TR5-6 thermistors by default TRn
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*/
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val = 0x55; /* thermal diode */
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w83795_write(W83795_REG_TEMP_CTRL2, val);
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/* Enable Digital Temperature Sensor */
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val = w83795_read(W83795_REG_TEMP_CTRL1);
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val |= W83795_REG_TEMP_CTRL1_EN_DTS; /* EN_DTS */
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w83795_write(W83795_REG_TEMP_CTRL1, val);
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}
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static void w83795_set_tfmr(w83795_fan_mode_t mode)
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{
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u8 val;
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u8 i;
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if ((mode == SMART_FAN_MODE) || (mode == THERMAL_CRUISE_MODE)) {
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val = 0xFF;
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} else {
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val = 0x00;
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}
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for (i = 0; i < 6; i++)
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w83795_write(W83795_REG_TFMR(i), val);
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}
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static u32 w83795_set_fan_mode(w83795_fan_mode_t mode)
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{
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if (mode == SPEED_CRUISE_MODE) {
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w83795_write(W83795_REG_FCMS1, 0xFF);
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printk(BIOS_INFO, "W83795G/ADG work in Speed Cruise Mode\n");
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} else {
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w83795_write(W83795_REG_FCMS1, 0x00);
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if (mode == THERMAL_CRUISE_MODE) {
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w83795_write(W83795_REG_FCMS2, 0x00);
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printk(BIOS_INFO, "W83795G/ADG work in Thermal Cruise Mode\n");
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} else if (mode == SMART_FAN_MODE) {
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w83795_write(W83795_REG_FCMS2, 0x3F);
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printk(BIOS_INFO, "W83795G/ADG work in Smart Fan Mode\n");
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} else {
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printk(BIOS_INFO, "W83795G/ADG work in Manual Mode\n");
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return -1;
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}
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}
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return 0;
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}
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static void w83795_set_tss(void)
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{
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u8 val;
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val = 0x00;
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w83795_write(W83795_REG_TSS(0), val); /* Temp1, 2 */
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w83795_write(W83795_REG_TSS(1), val); /* Temp3, 4 */
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w83795_write(W83795_REG_TSS(2), val); /* Temp5, 6 */
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}
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static void w83795_set_fan(w83795_fan_mode_t mode)
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{
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u8 i;
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/* select temperature sensor (TSS)*/
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w83795_set_tss();
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/* select Temperature to Fan mapping Relationships (TFMR)*/
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w83795_set_tfmr(mode);
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/* set fan output controlled mode (FCMS)*/
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w83795_set_fan_mode(mode);
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/* Set Critical Temperature to Full Speed all fan (CTFS) */
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for (i = 0; i < 6; i++) {
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w83795_write(W83795_REG_CTFS(i), 0x50); /* default 80 celsius degree */
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}
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if (mode == THERMAL_CRUISE_MODE) {
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/* Set Target Temperature of Temperature Inputs (TTTI) */
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for (i = 0; i < 6; i++) {
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w83795_write(W83795_REG_TTTI(i), 0x28); /* default 40 celsius degree */
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}
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} else if (mode == SMART_FAN_MODE) {
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/* Set the Relative Register-at SMART FAN IV Control Mode Table */
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//SFIV TODO
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}
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/* Set Hystersis of Temperature (HT) */
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//TODO
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}
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static void w83795_init(w83795_fan_mode_t mode, u8 dts_src)
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{
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u8 i;
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u8 val;
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if (do_smbus_read_byte(SMBUS_IO_BASE, W83795_DEV, 0x00) < 0) {
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printk(BIOS_ERR, "W83795G/ADG Nuvoton H/W Monitor not found\n");
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return;
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}
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val = w83795_read(W83795_REG_CONFIG);
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if ((val & W83795_REG_CONFIG_CONFIG48) == 0)
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printk(BIOS_INFO, "Found 64 pin W83795G Nuvoton H/W Monitor\n");
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else if ((val & W83795_REG_CONFIG_CONFIG48) == 1)
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printk(BIOS_INFO, "Found 48 pin W83795ADG Nuvoton H/W Monitor\n");
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/* Reset */
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val |= W83795_REG_CONFIG_INIT;
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w83795_write(W83795_REG_CONFIG, val);
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/* Fan monitoring setting */
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val = 0xFF; /* FAN1-FAN8 */
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w83795_write(W83795_REG_FANIN_CTRL1, val);
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val = 0x3F; /* FAN9-FAN14 */
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w83795_write(W83795_REG_FANIN_CTRL2, val);
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/* enable monitoring operations */
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val = w83795_read(W83795_REG_CONFIG);
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val |= W83795_REG_CONFIG_START;
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w83795_write(W83795_REG_CONFIG, val);
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w83795_dts_enable(dts_src);
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w83795_set_fan(mode);
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printk(BIOS_INFO, "Fan CTFS(celsius) TTTI(celsius)\n");
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for (i = 0; i < 6; i++) {
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val = w83795_read(W83795_REG_CTFS(i));
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printk(BIOS_INFO, " %x %d", i, val);
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val = w83795_read(W83795_REG_TTTI(i));
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printk(BIOS_INFO, " %d\n", val);
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}
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/* Temperature ReadOut */
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for (i = 0; i < 9; i++) {
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val = w83795_read(W83795_REG_DTS(i));
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printk(BIOS_DEBUG, "DTS%x ReadOut=%x \n", i, val);
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}
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}
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static void w83795_hwm_init(device_t dev)
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{
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struct device *cpu;
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struct cpu_info *info;
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info = cpu_info();
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cpu = info->cpu;
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if (!cpu)
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die("CPU: missing cpu device structure");
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if (cpu->vendor == X86_VENDOR_AMD)
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w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_AMD_SBTSI);
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else if (cpu->vendor == X86_VENDOR_INTEL)
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w83795_init(THERMAL_CRUISE_MODE, DTS_SRC_INTEL_PECI);
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else
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printk(BIOS_ERR, "Neither AMD nor INTEL CPU detected\n");
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}
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static void w83795_noop(device_t dummy)
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{
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}
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static struct device_operations w83795_operations = {
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.read_resources = w83795_noop,
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.set_resources = w83795_noop,
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.enable_resources = w83795_noop,
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.init = w83795_hwm_init,
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};
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static void enable_dev(device_t dev)
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{
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dev->ops = &w83795_operations;
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}
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struct chip_operations drivers_i2c_w83795_ops = {
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CHIP_NAME("Nuvoton W83795G/ADG Hardware Monitor")
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.enable_dev = enable_dev,
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};
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@ -0,0 +1,73 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _W83795_H_
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#define _W83795_H_
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#define W83795_DEV 0x2F /* Host I2c Addr (strap to addr1 addr0 1 1, 0x5E) */
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#define W83795_REG_I2C_ADDR 0xFC
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#define W83795_REG_BANKSEL 0x00
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#define W83795_REG_CONFIG 0x01
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#define W83795_REG_CONFIG_START 0x01
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#define W83795_REG_CONFIG_CONFIG48 0x04
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#define W83795_REG_CONFIG_INIT 0x80
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#define W83795_REG_TEMP_CTRL1 0x04 /* Temperature Monitoring Control Register */
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#define W83795_REG_TEMP_CTRL2 0x05 /* Temperature Monitoring Control Register */
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#define W83795_REG_FANIN_CTRL1 0x06
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#define W83795_REG_FANIN_CTRL2 0x07
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#define W83795_REG_TEMP_CTRL1_EN_DTS 0x20 /* Enable DTS (Digital Temperature Sensor) interface from INTEL PECI or AMD SB-TSI. */
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#define DTS_SRC_INTEL_PECI (0 << 0)
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#define DTS_SRC_AMD_SBTSI (1 << 0)
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#define W83795_REG_TSS(n) (0x209 + (n)) /* Temperature Source Selection Register */
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#define W83795_REG_TTTI(n) (0x260 + (n)) /* tarrget temperature W83795G/ADG will try to tune the fan output to keep */
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#define W83795_REG_CTFS(n) (0x268 + (n)) /* Critical Temperature to Full Speed all fan */
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#define W83795_REG_HT(n) (0x270 + (n)) /* Hystersis of Temperature */
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#define W83795_REG_DTSC 0x301 /* Digital Temperature Sensor Configuration */
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#define W83795_REG_DTSE 0x302 /* Digital Temperature Sensor Enable */
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#define W83795_REG_DTS(n) (0x26 + (n))
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#define W83795_REG_VRLSB 0x3C
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#define W83795_TEMP_REG_TR1 0x21
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#define W83795_TEMP_REG_TR2 0x22
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#define W83795_TEMP_REG_TR3 0x23
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#define W83795_TEMP_REG_TR4 0x24
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#define W83795_TEMP_REG_TR5 0x1F
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#define W83795_TEMP_REG_TR6 0x20
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#define W83795_REG_FCMS1 0x201
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#define W83795_REG_FCMS2 0x208
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#define W83795_REG_TFMR(n) (0x202 + (n)) /*temperature to fam mappig*/
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#define W83795_REG_DFSP 0x20C
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#define W83795_REG_FTSH(n) (0x240 + (n) * 2)
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#define W83795_REG_FTSL(n) (0x241 + (n) * 2)
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#define W83795_REG_TFTS 0x250
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typedef enum w83795_fan_mode {
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SPEED_CRUISE_MODE, ///< Fan Speed Cruise mode keeps the fan speed in a specified range
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THERMAL_CRUISE_MODE, ///< Thermal Cruise mode is an algorithm to control the fan speed to keep the temperature source around the TTTI
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SMART_FAN_MODE, ///< Smart Fan mode offers 6 slopes to control the fan speed
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MANUAL_MODE, ///< control manually
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} w83795_fan_mode_t;
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#endif
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@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS
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select SOUTHBRIDGE_AMD_CIMX_SB700
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select SUPERIO_WINBOND_W83627DHG
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select SUPERIO_NUVOTON_WPCM450
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select DRIVERS_I2C_W83795
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select UDELAY_TSC
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select BOARD_HAS_FADT
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select HAVE_BUS_CONFIG
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@ -84,8 +84,8 @@ chip northbridge/amd/agesa/family15/root_complex
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irq 0x70 = 0x01 #keyboard
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irq 0x72 = 0x0C #mouse
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end
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#device pnp 2e.6 off # SPI
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#end
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device pnp 2e.6 off # SPI
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end
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device pnp 2e.307 off # GPIO6
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end
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device pnp 2e.8 off # WDTO#, PLED
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@ -106,6 +106,10 @@ chip northbridge/amd/agesa/family15/root_complex
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device pnp 2e.c off # PECI, SST
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end
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end #superio/winbond/w83627dhg
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chip drivers/i2c/w83795
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device pnp 5e on #hwm
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end
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end #drivers/i2c/w83795
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end # LPC
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device pci 14.4 on end # PCI 0x4384
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device pci 14.5 on end # USB 3
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@ -90,6 +90,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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}
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post_code(0x3C);
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/* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default.
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* In order to access W83795G/ADG HWM using I2C protocol,
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* we select function to SDA, SCL function (or GP33, GP32 function).
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*/
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w83627dhg_enable_i2c(PNP_DEV(0x2E, W83627DHG_SPI));
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nb_Ht_Init();
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post_code(0x3D);
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/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
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