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mb/google/sarien/variants/arcada: Set tcc offset value 

Set tcc offset value to 1 degree celsius for Arcada system.

BRANCH=None
BUG=b:122636962
TEST=Built and tested on Arcada system

Signed-off-by: Bonnie Lin <bonnie_ty_lin@wistron.corp-partner.google.com>
Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This commit is contained in:
Bonnie Lin 2019-05-08 18:08:08 +08:00 committed by Patrick Georgi
parent bddfa59f1d
commit 1360b9a73f
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/sarien/variants/arcada/devicetree.cb
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@ -161,7 +161,7 @@ chip soc/intel/cannonlake
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
register "tcc_offset" = "10"
register "tcc_offset" = "1"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,