arm64: Replace CONFIG_* variables with {read/write}_current
Instead of relying on config variables to determine the current el, use {read/write}_current macros for accessing registers. BUG=chrome-os-partner:30785 BRANCH=None TEST=Compiles successfully and boots to kernel login prompt Change-Id: I6c27571fa65e06e28b71fee3e21d6ca93542e66b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 96aed53b2879310f6f979d5aa78b8d1df7f04564 Original-Change-Id: If4a5d1e9aa50ab180c8012862e2a6c37384f7f91 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/217148 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9065 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -13,15 +13,3 @@ config ARCH_ROMSTAGE_ARMV8_64
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config ARCH_RAMSTAGE_ARMV8_64
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config ARCH_RAMSTAGE_ARMV8_64
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def_bool n
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def_bool n
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select ARCH_RAMSTAGE_ARM64
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select ARCH_RAMSTAGE_ARM64
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config ARM64_CPUS_START_IN_EL3
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def_bool n
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depends on ARCH_BOOTBLOCK_ARM_V8_64 || ARCH_ROMSTAGE_ARM_V8_64 || ARCH_RAMSTAGE_ARM_V8_64
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config ARM64_CPUS_START_IN_EL2
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def_bool n
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depends on ARCH_BOOTBLOCK_ARM_V8_64 || ARCH_ROMSTAGE_ARM_V8_64 || ARCH_RAMSTAGE_ARM_V8_64
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config ARM64_CPUS_START_IN_EL1
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def_bool n
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depends on ARCH_BOOTBLOCK_ARM_V8_64 || ARCH_ROMSTAGE_ARM_V8_64 || ARCH_RAMSTAGE_ARM_V8_64
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@ -19,16 +19,8 @@
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#include <arch/asm.h>
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#include <arch/asm.h>
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#define __ASSEMBLY__
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#if CONFIG_ARM64_CPUS_START_IN_EL3
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#include <arch/lib_helpers.h>
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#define SCTLR_ELx sctlr_el3
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#elif CONFIG_ARM64_CPUS_START_IN_EL2
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#define SCTLR_ELx sctlr_el2
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#elif CONFIG_ARM64_CPUS_START_IN_EL1
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#define SCTLR_ELx sctlr_el1
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#else
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#error Need to know what ELx processor starts up in.
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#endif
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#define STACK_SZ CONFIG_STACK_SIZE
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#define STACK_SZ CONFIG_STACK_SIZE
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#define EXCEPTION_STACK_SZ CONFIG_STACK_SIZE
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#define EXCEPTION_STACK_SZ CONFIG_STACK_SIZE
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@ -109,12 +101,12 @@ ENTRY(arm64_c_environment)
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ENDPROC(arm64_c_environment)
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ENDPROC(arm64_c_environment)
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CPU_RESET_ENTRY(arm64_cpu_startup)
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CPU_RESET_ENTRY(arm64_cpu_startup)
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mrs x0, SCTLR_ELx
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read_current x0, sctlr
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bic x0, x0, #(1 << 25) /* Little Endian */
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bic x0, x0, #(1 << 25) /* Little Endian */
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bic x0, x0, #(1 << 19) /* XN not enforced */
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bic x0, x0, #(1 << 19) /* XN not enforced */
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bic x0, x0, #(1 << 12) /* Disable Instruction Cache */
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bic x0, x0, #(1 << 12) /* Disable Instruction Cache */
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bic x0, x0, #0xf /* Clear SA, C, A, and M */
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bic x0, x0, #0xf /* Clear SA, C, A, and M */
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msr SCTLR_ELx, x0
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write_current sctlr, x0, x1
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isb
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isb
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b arm64_c_environment
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b arm64_c_environment
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ENDPROC(arm64_cpu_startup)
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ENDPROC(arm64_cpu_startup)
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@ -5,7 +5,6 @@ config SOC_NVIDIA_TEGRA132
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select ARCH_VERSTAGE_ARMV4
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select ARCH_VERSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV4
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select ARCH_ROMSTAGE_ARMV4
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select ARCH_RAMSTAGE_ARMV8_64
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select ARCH_RAMSTAGE_ARMV8_64
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select ARM64_CPUS_START_IN_EL3
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select BOOTBLOCK_CONSOLE
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select BOOTBLOCK_CONSOLE
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select HAVE_MONOTONIC_TIMER
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select HAVE_MONOTONIC_TIMER
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select HAVE_HARD_RESET
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select HAVE_HARD_RESET
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